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Searched refs:ctrl3 (Results 1 – 6 of 6) sorted by relevance

/drivers/crypto/bcm/
A Dspu2.c563 u64 ctrl3; in spu2_fmd_init() local
588 ctrl3 = 0; in spu2_fmd_init()
593 fmd->ctrl3 = cpu_to_le64(ctrl3); in spu2_fmd_init()
763 u64 ctrl3; in spu2_fmd_ctrl3_write() local
767 fmd->ctrl3 = cpu_to_le64(ctrl3); in spu2_fmd_ctrl3_write()
809 u64 ctrl3; in spu2_payload_length() local
811 ctrl3 = le64_to_cpu(fmd->ctrl3); in spu2_payload_length()
1192 u64 ctrl3; in spu2_cipher_req_finish() local
1222 ctrl3 = le64_to_cpu(fmd->ctrl3); in spu2_cipher_req_finish()
1224 ctrl3 |= data_size; in spu2_cipher_req_finish()
[all …]
A Dspu2.h79 __le64 ctrl3; member
/drivers/media/i2c/
A Dov2659.c183 u8 ctrl3; member
702 static const struct pll_ctrl_reg ctrl3[] = { variable
904 for (j = 0; ctrl3[j].div != 0; j++) { in ov2659_pll_calc_params()
905 prediv = ctrl3[j].div; in ov2659_pll_calc_params()
918 ctrl3_reg = ctrl3[j].reg; in ov2659_pll_calc_params()
926 ov2659->pll.ctrl3 = ctrl3_reg; in ov2659_pll_calc_params()
939 {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3}, in ov2659_set_pixel_clock()
/drivers/net/ethernet/stmicro/stmmac/
A Ddwmac4_core.c98 u32 ctrl2, ctrl3; in dwmac4_rx_queue_priority() local
102 ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3); in dwmac4_rx_queue_priority()
112 ctrl3 &= ~clear_mask; in dwmac4_rx_queue_priority()
122 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3); in dwmac4_rx_queue_priority()
126 ctrl3 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) & in dwmac4_rx_queue_priority()
129 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3); in dwmac4_rx_queue_priority()
A Ddwxgmac2_core.c103 u32 ctrl2, ctrl3; in dwxgmac2_rx_queue_prio() local
107 ctrl3 = readl(ioaddr + XGMAC_RXQ_CTRL3); in dwxgmac2_rx_queue_prio()
117 ctrl3 &= ~clear_mask; in dwxgmac2_rx_queue_prio()
127 writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3); in dwxgmac2_rx_queue_prio()
131 ctrl3 |= (prio << XGMAC_PSRQ_SHIFT(queue)) & in dwxgmac2_rx_queue_prio()
134 writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3); in dwxgmac2_rx_queue_prio()
/drivers/net/ethernet/marvell/mvpp2/
A Dmvpp2_main.c4571 u32 ctrl3; in mvpp22_mode_reconfigure() local
4588 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure()
4589 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; in mvpp22_mode_reconfigure()
4592 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; in mvpp22_mode_reconfigure()
4594 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; in mvpp22_mode_reconfigure()
4596 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure()

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