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Searched refs:ctrl_base (Results 1 – 24 of 24) sorted by relevance

/drivers/phy/broadcom/
A Dphy-brcm-usb-init.c469 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_read()
471 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_read()
475 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_read()
508 USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB); in brcmusb_usb_phy_ldo_fix()
511 USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB); in brcmusb_usb_phy_ldo_fix()
678 brcmusb_usb3_pll_fix(ctrl_base); in brcmusb_usb3_phy_workarounds()
680 brcmusb_usb3_ssc_enable(ctrl_base); in brcmusb_usb3_phy_workarounds()
681 brcmusb_usb3_enable_pipe_reset(ctrl_base); in brcmusb_usb3_phy_workarounds()
682 brcmusb_usb3_enable_sigdet(ctrl_base); in brcmusb_usb3_phy_workarounds()
683 brcmusb_usb3_enable_skip_align(ctrl_base); in brcmusb_usb3_phy_workarounds()
[all …]
A Dphy-brcm-sata.c74 void __iomem *ctrl_base; member
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
431 void __iomem *ctrl_base = brcm_sata_ctrl_base(port); in brcm_ns2_sata_init() local
462 writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1); in brcm_ns2_sata_init()
464 writel(0x0, ctrl_base + PHY_CTRL_1); in brcm_ns2_sata_init()
780 priv->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "phy-ctrl"); in brcm_sata_phy_probe()
781 if (IS_ERR(priv->ctrl_base)) in brcm_sata_phy_probe()
782 return PTR_ERR(priv->ctrl_base); in brcm_sata_phy_probe()
/drivers/fsi/
A Dfsi-master-aspeed.c34 static const u32 ctrl_base = 0x80000000; variable
242 ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0, in check_errors()
401 opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); in aspeed_master_init()
406 opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); in aspeed_master_init()
409 opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg); in aspeed_master_init()
417 opb_writel(aspeed, ctrl_base + FSI_MMODE, reg); in aspeed_master_init()
420 opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg); in aspeed_master_init()
423 opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg); in aspeed_master_init()
428 opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg); in aspeed_master_init()
430 opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL); in aspeed_master_init()
[all …]
/drivers/video/fbdev/riva/
A Dnv_driver.c319 (volatile U032 __iomem *)(par->ctrl_base + 0x00680000); in riva_common_setup()
321 (volatile U032 __iomem *)(par->ctrl_base + 0x00100000); in riva_common_setup()
323 (volatile U032 __iomem *)(par->ctrl_base + 0x00002000); in riva_common_setup()
325 (volatile U032 __iomem *)(par->ctrl_base + 0x00400000); in riva_common_setup()
327 (volatile U032 __iomem *)(par->ctrl_base + 0x00101000); in riva_common_setup()
329 (volatile U032 __iomem *)(par->ctrl_base + 0x00009000); in riva_common_setup()
331 (volatile U032 __iomem *)(par->ctrl_base + 0x00000000); in riva_common_setup()
333 (volatile U032 __iomem *)(par->ctrl_base + 0x00800000); in riva_common_setup()
334 par->riva.PCIO0 = par->ctrl_base + 0x00601000; in riva_common_setup()
335 par->riva.PDIO0 = par->ctrl_base + 0x00681000; in riva_common_setup()
[all …]
A Drivafb.h48 u8 __iomem *ctrl_base; /* virtual control register base addr */ member
A Dfbdev.c1966 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, in rivafb_probe()
1968 if (!default_par->ctrl_base) { in rivafb_probe()
1992 (u32 __iomem *)(default_par->ctrl_base + 0x00600000); in rivafb_probe()
1994 (u32 __iomem *)(default_par->ctrl_base + 0x00710000); in rivafb_probe()
2064 iounmap(default_par->ctrl_base); in rivafb_probe()
2092 iounmap(par->ctrl_base); in rivafb_remove()
/drivers/media/platform/verisilicon/
A Dimx8m_vpu_hw.c33 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
35 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
40 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
42 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
49 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
51 writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
68 writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE); in imx8mq_runtime_resume()
69 writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE); in imx8mq_runtime_resume()
70 writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE); in imx8mq_runtime_resume()
257 vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; in imx8mq_vpu_hw_init()
A Dhantro.h208 void __iomem *ctrl_base; member
/drivers/mailbox/
A Dmailbox-mpfs.c69 void __iomem *ctrl_base; member
85 status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); in mpfs_mbox_busy()
108 val = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); in mpfs_mbox_last_tx_done()
161 writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET); in mpfs_mbox_send_data()
264 mbox->ctrl_base = devm_platform_ioremap_resource(pdev, 0); in mpfs_mbox_old_format_probe()
265 if (IS_ERR(mbox->ctrl_base)) in mpfs_mbox_old_format_probe()
266 return PTR_ERR(mbox->ctrl_base); in mpfs_mbox_old_format_probe()
274 mbox->mbox_base = mbox->ctrl_base + MAILBOX_REG_OFFSET; in mpfs_mbox_old_format_probe()
/drivers/usb/musb/
A Dmusb_dsps.c173 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable()
199 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable()
317 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt()
419 glue->regset.base = musb->ctrl_base; in dsps_musb_dbg_init()
440 musb->ctrl_base = reg_base; in dsps_musb_init()
515 void __iomem *ctrl_base = musb->ctrl_base; in dsps_musb_set_mode() local
518 reg = musb_readl(ctrl_base, wrp->mode); in dsps_musb_set_mode()
531 musb_writel(ctrl_base, wrp->mode, reg); in dsps_musb_set_mode()
544 musb_writel(ctrl_base, wrp->mode, reg); in dsps_musb_set_mode()
988 mbase = musb->ctrl_base; in dsps_suspend()
[all …]
A Dtusb6010.c51 void __iomem *tbase = musb->ctrl_base; in tusb_get_revision()
68 void __iomem *tbase = musb->ctrl_base; in tusb_print_revision()
101 void __iomem *tbase = musb->ctrl_base; in tusb_wbus_quirk()
333 void __iomem *tbase = musb->ctrl_base; in tusb_draw_power()
369 void __iomem *tbase = musb->ctrl_base; in tusb_set_clock_source()
396 void __iomem *tbase = musb->ctrl_base; in tusb_allow_idle()
433 void __iomem *tbase = musb->ctrl_base; in tusb_musb_vbus_status()
558 void __iomem *tbase = musb->ctrl_base; in tusb_musb_set_vbus()
635 void __iomem *tbase = musb->ctrl_base; in tusb_musb_set_mode()
827 void __iomem *tbase = musb->ctrl_base; in tusb_musb_interrupt()
[all …]
A Dda8xx.c88 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_enable()
107 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_disable()
167 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG, in otg_timer()
228 musb_writel(musb->ctrl_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); in da8xx_babble_recover()
235 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_interrupt()
360 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_init()
453 void __iomem *reg_base = musb->ctrl_base; in da8xx_dma_controller_callback()
A Dmusb_cppi41.c359 musb_writel(musb->ctrl_base, USB_CTRL_TX_MODE, new_mode); in cppi41_set_dma_mode()
362 musb_writel(musb->ctrl_base, USB_CTRL_RX_MODE, new_mode); in cppi41_set_dma_mode()
388 musb_writel(musb->ctrl_base, DA8XX_USB_MODE, new_mode); in da8xx_set_dma_mode()
407 musb_writel(controller->controller.musb->ctrl_base, in cppi41_set_autoreq_mode()
439 musb_writel(musb->ctrl_base, in cppi41_configure_channel()
449 musb_writel(musb->ctrl_base, in cppi41_configure_channel()
626 musb_writel(musb->ctrl_base, controller->tdown_reg, in cppi41_dma_channel_abort()
632 musb_writel(musb->ctrl_base, controller->tdown_reg, tdbit); in cppi41_dma_channel_abort()
A Dtusb6010_omap.c585 void __iomem *tbase = musb->ctrl_base; in tusb_dma_controller_create()
591 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); in tusb_dma_controller_create()
592 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); in tusb_dma_controller_create()
604 tusb_dma->tbase = musb->ctrl_base; in tusb_dma_controller_create()
A Dmusb_core.h324 void __iomem *ctrl_base; member
A Dmusb_core.c2162 musb->ctrl_base = mbase; in allocate_instance()
/drivers/leds/
A Dleds-sc27xx-bltc.c90 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_enable() local
102 return regmap_update_bits(regmap, ctrl_base, in sc27xx_led_enable()
110 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_disable() local
113 return regmap_update_bits(regmap, ctrl_base, in sc27xx_led_disable()
151 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_pattern_clear() local
161 err = regmap_update_bits(regmap, ctrl_base, in sc27xx_led_pattern_clear()
177 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_pattern_set() local
229 err = regmap_update_bits(regmap, ctrl_base, in sc27xx_led_pattern_set()
/drivers/spi/
A Dspi-ti-qspi.c47 struct regmap *ctrl_base; member
530 if (qspi->ctrl_base) { in ti_qspi_enable_memory_map()
531 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_enable_memory_map()
544 if (qspi->ctrl_base) in ti_qspi_disable_memory_map()
545 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_disable_memory_map()
831 qspi->ctrl_base = in ti_qspi_probe()
834 if (IS_ERR(qspi->ctrl_base)) { in ti_qspi_probe()
835 ret = PTR_ERR(qspi->ctrl_base); in ti_qspi_probe()
/drivers/dma/
A Ddma-jz4780.c151 void __iomem *ctrl_base; member
198 return readl(jzdma->ctrl_base + reg); in jz4780_dma_ctrl_readl()
204 writel(val, jzdma->ctrl_base + reg); in jz4780_dma_ctrl_writel()
884 jzdma->ctrl_base = devm_ioremap_resource(dev, res); in jz4780_dma_probe()
885 if (IS_ERR(jzdma->ctrl_base)) in jz4780_dma_probe()
886 return PTR_ERR(jzdma->ctrl_base); in jz4780_dma_probe()
893 jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET; in jz4780_dma_probe()
A Dfsl-qdma.c218 void __iomem *ctrl_base; member
590 void __iomem *block, *ctrl = fsl_qdma->ctrl_base; in fsl_qdma_halt()
772 void __iomem *block, *ctrl = fsl_qdma->ctrl_base; in fsl_qdma_queue_handler()
877 void __iomem *block, *ctrl = fsl_qdma->ctrl_base; in fsl_qdma_reg_init()
1188 fsl_qdma->ctrl_base = devm_platform_ioremap_resource(pdev, 0); in fsl_qdma_probe()
1189 if (IS_ERR(fsl_qdma->ctrl_base)) in fsl_qdma_probe()
1190 return PTR_ERR(fsl_qdma->ctrl_base); in fsl_qdma_probe()
/drivers/perf/
A Darm-cci.c98 void __iomem *ctrl_base; member
370 rev = readl_relaxed(cci_pmu->ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK; in probe_cci400_revision()
668 val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) | CCI_PMCR_CEN; in __cci_pmu_enable_nosync()
669 writel(val, cci_pmu->ctrl_base + CCI_PMCR); in __cci_pmu_enable_nosync()
685 val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN; in __cci_pmu_disable()
686 writel(val, cci_pmu->ctrl_base + CCI_PMCR); in __cci_pmu_disable()
782 return (readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & in pmu_get_max_counters()
1596 cci_pmu->ctrl_base = *(void __iomem **)dev->platform_data; in cci_pmu_alloc()
/drivers/gpu/drm/msm/dsi/
A Ddsi_host.c110 void __iomem *ctrl_base; member
193 return readl(msm_host->ctrl_base + reg); in dsi_read()
198 writel(data, msm_host->ctrl_base + reg); in dsi_write()
225 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); in dsi_get_config()
1651 if (!msm_host->ctrl_base) in dsi_host_irq()
1960 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); in msm_dsi_host_init()
1961 if (IS_ERR(msm_host->ctrl_base)) in msm_dsi_host_init()
1962 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->ctrl_base), in msm_dsi_host_init()
1980 msm_host->ctrl_base += cfg->io_offset; in msm_dsi_host_init()
2577 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); in msm_dsi_host_snapshot()
/drivers/net/ethernet/ti/
A Ddavinci_emac.c315 void __iomem *ctrl_base; member
361 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
362 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
1868 priv->ctrl_base = in davinci_emac_probe()
1870 if (IS_ERR(priv->ctrl_base)) { in davinci_emac_probe()
1871 rc = PTR_ERR(priv->ctrl_base); in davinci_emac_probe()
1875 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; in davinci_emac_probe()
/drivers/net/ethernet/hisilicon/
A Dhix5hd2_gmac.c250 void __iomem *ctrl_base; member
316 writel_relaxed(val, priv->ctrl_base); in hix5hd2_config_port()
1121 priv->ctrl_base = devm_platform_ioremap_resource(pdev, 1); in hix5hd2_dev_probe()
1122 if (IS_ERR(priv->ctrl_base)) { in hix5hd2_dev_probe()
1123 ret = PTR_ERR(priv->ctrl_base); in hix5hd2_dev_probe()

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