Searched refs:ctrl_offset (Results 1 – 9 of 9) sorted by relevance
| /drivers/thermal/ |
| A D | k3_bandgap.c | 88 u32 ctrl_offset; member
203 data[id].ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + in k3_bandgap_probe()
205 data[id].stat_offset = data[id].ctrl_offset + 0x8; in k3_bandgap_probe()
207 val = readl(data[id].bgp->base + data[id].ctrl_offset); in k3_bandgap_probe()
212 writel(val, data[id].bgp->base + data[id].ctrl_offset); in k3_bandgap_probe()
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| A D | k3_j72xx_bandgap.c | 187 u32 ctrl_offset; member
350 val = readl(bgp->cfg2_base + data->ctrl_offset); in k3_j72xx_bandgap_init_hw()
354 writel(val, bgp->cfg2_base + data->ctrl_offset); in k3_j72xx_bandgap_init_hw()
484 data[id].ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + id * 0x20; in k3_j72xx_bandgap_probe()
485 data[id].stat_offset = data[id].ctrl_offset + in k3_j72xx_bandgap_probe()
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| /drivers/reset/ |
| A D | reset-lpc18xx.c | 71 u32 ctrl_offset = LPC18XX_RGU_CTRL0; in lpc18xx_rgu_setclear_reset() local
76 ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32); in lpc18xx_rgu_setclear_reset()
82 writel(stat | rst_bit, rc->base + ctrl_offset); in lpc18xx_rgu_setclear_reset()
84 writel(stat & ~rst_bit, rc->base + ctrl_offset); in lpc18xx_rgu_setclear_reset()
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| A D | reset-npcm.c | 122 unsigned int ctrl_offset = id >> 8; in npcm_rc_setclear_reset() local
127 stat = readl(rc->base + ctrl_offset); in npcm_rc_setclear_reset()
129 writel(stat | rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
131 writel(stat & ~rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
153 unsigned int ctrl_offset = id >> 8; in npcm_rc_status() local
155 return (readl(rc->base + ctrl_offset) & rst_bit); in npcm_rc_status()
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| /drivers/clk/sophgo/ |
| A D | clk-sg2044-pll.c | 65 u32 ctrl_offset; member
147 pll->syscon_offset + pll->pll.ctrl_offset + PLL_HIGH_CTRL_OFFSET, in sg2044_pll_recalc_rate()
331 pll->syscon_offset + pll->pll.ctrl_offset, in sg2044_pll_update_vcosel()
366 pll->syscon_offset + pll->pll.ctrl_offset + in sg2044_pll_set_rate()
403 .ctrl_offset = (_ctrl_offset), \
424 .ctrl_offset = (_ctrl_offset), \
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| /drivers/pinctrl/mediatek/ |
| A D | mtk-eint.c | 335 unsigned int rst, ctrl_offset; in mtk_eint_debounce_process() local
340 ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_ctrl; in mtk_eint_debounce_process()
341 dbnc = readl(eint->base[inst] + ctrl_offset); in mtk_eint_debounce_process()
344 ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_set; in mtk_eint_debounce_process()
346 writel(rst, eint->base[inst] + ctrl_offset); in mtk_eint_debounce_process()
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| /drivers/dma/xilinx/ |
| A D | xilinx_dma.c | 423 u32 ctrl_offset; member
532 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
554 return dma_read(chan, chan->ctrl_offset + reg); in dma_ctrl_read()
560 dma_write(chan, chan->ctrl_offset + reg, value); in dma_ctrl_write()
598 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); in dma_writeq()
2870 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; in xilinx_dma_chan_probe()
2895 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2897 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| A D | dma.c | 383 static bool _dma64_addrext(struct dma_info *di, uint ctrl_offset) in _dma64_addrext() argument
386 bcma_set32(di->core, ctrl_offset, D64_XC_AE); in _dma64_addrext()
387 w = bcma_read32(di->core, ctrl_offset); in _dma64_addrext()
388 bcma_mask32(di->core, ctrl_offset, ~D64_XC_AE); in _dma64_addrext()
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| /drivers/net/ethernet/netronome/nfp/ |
| A D | nfp_net_common.c | 555 nfp_net_aux_irq_request(struct nfp_net *nn, u32 ctrl_offset, in nfp_net_aux_irq_request() argument
571 nn_writeb(nn, ctrl_offset, entry->entry); in nfp_net_aux_irq_request()
583 static void nfp_net_aux_irq_free(struct nfp_net *nn, u32 ctrl_offset, in nfp_net_aux_irq_free() argument
586 nn_writeb(nn, ctrl_offset, 0xff); in nfp_net_aux_irq_free()
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