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Searched refs:ctx_reg (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/gt/
A Dintel_gt_regs.h230 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) argument
231 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) argument
232 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) argument
233 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) argument
234 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) argument
235 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) argument
236 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ argument
237 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
/drivers/spi/
A Dspi-ti-qspi.c52 struct ti_qspi_regs ctx_reg; member
172 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_setup_clk() local
184 if (ctx_reg->clkctrl != clk_ctrl_new) { in ti_qspi_setup_clk()
194 ctx_reg->clkctrl = clk_ctrl_new; in ti_qspi_setup_clk()
202 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_restore_ctx() local
204 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_restore_ctx()
/drivers/gpu/drm/nouveau/nvkm/engine/gr/
A Dnv04.c1135 static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg) in ctx_reg() function
1198 *ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31; in nv04_gr_chan_new()

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