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Searched refs:cur0_ctl (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_cm.c119 dpp_base->att.cur0_ctl.bits.expansion_mode = 0; in dpp401_set_cursor_attributes()
120 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en; in dpp401_set_cursor_attributes()
121 dpp_base->att.cur0_ctl.bits.mode = color_format; in dpp401_set_cursor_attributes()
134 if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) { in dpp401_set_cursor_position()
137 dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; in dpp401_set_cursor_position()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dcursor_reg_cache.h87 union reg_cur0_control_cfg cur0_ctl; member
91 union reg_cur0_control_cfg cur0_ctl; member
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp.c486 if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) { in dpp1_set_cursor_position()
489 dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; in dpp1_set_cursor_position()
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp.c412 dpp_base->att.cur0_ctl.bits.expansion_mode = 0; in dpp3_set_cursor_attributes()
413 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en; in dpp3_set_cursor_attributes()
414 dpp_base->att.cur0_ctl.bits.mode = color_format; in dpp3_set_cursor_attributes()
/drivers/gpu/drm/amd/display/dc/
A Ddc_dmub_srv.c1063 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; in dc_build_cursor_position_update_payload0()
1079 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; in dc_build_cursor_attribute_update_payload1()
/drivers/gpu/drm/amd/display/dmub/inc/
A Ddmub_cmd.h3696 union dmub_reg_cur0_control_cfg cur0_ctl; member
3729 union dmub_reg_cur0_control_cfg cur0_ctl; member

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