| /drivers/gpu/drm/ttm/ |
| A D | ttm_bo_util.c | 808 curs->needs_unlock = false; in ttm_lru_walk_trylock()
811 curs->needs_unlock = true; in ttm_lru_walk_trylock()
836 curs->needs_unlock = true; in ttm_lru_walk_ticketlock()
911 if (curs->needs_unlock) in ttm_bo_lru_cursor_cleanup_bo()
914 curs->bo = NULL; in ttm_bo_lru_cursor_cleanup_bo()
949 memset(curs, 0, sizeof(*curs)); in ttm_bo_lru_cursor_init()
951 curs->arg = arg; in ttm_bo_lru_cursor_init()
953 return curs; in ttm_bo_lru_cursor_init()
964 bool first = !curs->bo; in __ttm_bo_lru_cursor_next()
989 if (curs->needs_unlock) in __ttm_bo_lru_cursor_next()
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| /drivers/gpu/drm/nouveau/dispnv50/ |
| A D | head917d.c | 90 NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | in head917d_curs_set()
91 NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in head917d_curs_set()
96 HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); in head917d_curs_set()
98 PUSH_MTHD(push, NV917D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle); in head917d_curs_set()
107 case 32: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break; in head917d_curs_layout()
108 case 64: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break; in head917d_curs_layout()
109 case 128: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128; break; in head917d_curs_layout()
110 case 256: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256; break; in head917d_curs_layout()
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| A D | curs507a.c | 83 if (asyh->curs.handle != handle || asyh->curs.offset != offset) { in curs507a_prepare()
84 asyh->curs.handle = handle; in curs507a_prepare()
85 asyh->curs.offset = offset; in curs507a_prepare()
86 asyh->set.curs = asyh->curs.visible; in curs507a_prepare()
94 asyh->curs.visible = false; in curs507a_release()
110 asyh->curs.visible = asyw->state.visible; in curs507a_acquire()
111 if (ret || !asyh->curs.visible) in curs507a_acquire()
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| A D | head.c | 49 if (clr.curs) head->func->curs_clr(head); in nv50_head_flush_clr()
401 asyh->curs.visible = false; in nv50_head_atomic_check()
415 if (asyh->curs.visible) { in nv50_head_atomic_check()
416 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs))) in nv50_head_atomic_check()
417 asyh->set.curs = true; in nv50_head_atomic_check()
419 if (armh->curs.visible) { in nv50_head_atomic_check()
420 asyh->clr.curs = true; in nv50_head_atomic_check()
433 asyh->clr.curs = armh->curs.visible; in nv50_head_atomic_check()
436 asyh->set.curs = asyh->curs.visible; in nv50_head_atomic_check()
476 asyh->curs = armh->curs; in nv50_head_atomic_duplicate_state()
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| A D | head507d.c | 151 NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | in head507d_curs_set()
152 NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in head507d_curs_set()
158 HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); in head507d_curs_set()
167 case 0xcf: asyh->curs.format = NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8; break; in head507d_curs_format()
180 case 32: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break; in head507d_curs_layout()
181 case 64: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break; in head507d_curs_layout()
241 asyh->set.curs = asyh->curs.visible; in head507d_core_set()
257 (asyh->core.visible = asyh->curs.visible)) { in head507d_core_calc()
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| A D | head827d.c | 60 NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | in head827d_curs_set()
61 NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in head827d_curs_set()
67 HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); in head827d_curs_set()
69 PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle); in head827d_curs_set()
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| A D | headc37d.c | 134 NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | in headc37d_curs_set()
135 NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in headc37d_curs_set()
148 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle); in headc37d_curs_set()
149 PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8); in headc37d_curs_set()
157 asyh->curs.format = asyw->image.format; in headc37d_curs_format()
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| A D | headca7d.c | 135 const u32 curs_hi = upper_32_bits(asyh->curs.offset); in headca7d_curs_set()
136 const u32 curs_lo = lower_32_bits(asyh->curs.offset); in headca7d_curs_set()
153 NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | in headca7d_curs_set()
154 NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in headca7d_curs_set()
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| A D | atom.h | 89 } curs; member
137 bool curs:1; member
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| A D | head907d.c | 183 NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | in head907d_curs_set()
184 NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in head907d_curs_set()
189 HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); in head907d_curs_set()
191 PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle); in head907d_curs_set()
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| A D | Kbuild | 53 nouveau-y += dispnv50/curs.o
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| /drivers/gpu/drm/xe/ |
| A D | xe_pt.c | 307 struct xe_res_cursor *curs; member
468 struct xe_res_cursor curs = *xe_walk->curs; in xe_pt_scan_64K() local
482 if (!IS_ALIGNED(xe_res_dma(&curs), SZ_64K) || curs.size < SZ_64K) in xe_pt_scan_64K()
485 xe_res_next(&curs, SZ_64K); in xe_pt_scan_64K()
531 struct xe_res_cursor *curs = xe_walk->curs; in xe_pt_stage_bind_entry() local
541 xe_res_dma(curs) + in xe_pt_stage_bind_entry()
698 struct xe_res_cursor curs; in xe_pt_stage_bind() local
709 .curs = &curs, in xe_pt_stage_bind()
730 &curs); in xe_pt_stage_bind()
760 xe_vma_size(vma), &curs); in xe_pt_stage_bind()
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| A D | xe_shrinker.c | 67 struct ttm_bo_lru_cursor curs; in __xe_shrinker_walk() local
77 ttm_bo_lru_for_each_reserved_guarded(&curs, man, &arg, ttm_bo) { in __xe_shrinker_walk()
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| /drivers/video/console/ |
| A D | vgacon.c | 478 int curs, cure; in vgacon_set_cursor_size() local
488 curs = inb_p(vga_video_port_val); in vgacon_set_cursor_size()
492 curs = 0; in vgacon_set_cursor_size()
496 curs = (curs & 0xc0) | from; in vgacon_set_cursor_size()
500 outb_p(curs, vga_video_port_val); in vgacon_set_cursor_size()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ |
| A D | tu1xx.c | 19 .curs = TU102_DISP_CURSOR,
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| A D | ad10x.c | 19 .curs = GA102_DISP_CURSOR,
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| A D | ga1xx.c | 19 .curs = GA102_DISP_CURSOR,
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| A D | gb20x.c | 20 .curs = GB202_DISP_CURSOR,
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| A D | gpu.h | 17 u32 curs; member
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| /drivers/net/hamradio/ |
| A D | baycom_ser_fdx.c | 191 …er12_rx(struct net_device *dev, struct baycom_state *bc, struct timespec64 *ts, unsigned char curs) in ser12_rx() argument
224 if (bc->modem.ser12.last_rxbit != curs) { in ser12_rx()
225 bc->modem.ser12.last_rxbit = curs; in ser12_rx()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ |
| A D | disp.c | 1766 rm->user[4].base.oclass = gpu->disp.class.curs; in r535_disp_new()
|