Searched refs:cw3 (Results 1 – 14 of 14) sorted by relevance
| /drivers/gpu/drm/amd/display/dmub/src/ |
| A D | dmub_dcn30.c | 124 const struct dmub_window *cw3, in dmub_dcn30_setup_windows() argument
150 offset = cw3->offset; in dmub_dcn30_setup_windows()
154 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); in dmub_dcn30_setup_windows()
156 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, in dmub_dcn30_setup_windows()
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| A D | dmub_dcn20.c | 191 const struct dmub_window *cw3, in dmub_dcn20_setup_windows() argument
219 dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows()
223 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); in dmub_dcn20_setup_windows()
225 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, in dmub_dcn20_setup_windows()
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| A D | dmub_dcn31.c | 192 const struct dmub_window *cw3, in dmub_dcn31_setup_windows() argument
200 offset = cw3->offset; in dmub_dcn31_setup_windows()
204 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); in dmub_dcn31_setup_windows()
206 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, in dmub_dcn31_setup_windows()
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| A D | dmub_dcn30.h | 43 const struct dmub_window *cw3,
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| A D | dmub_dcn35.c | 219 const struct dmub_window *cw3, in dmub_dcn35_setup_windows() argument
227 offset = cw3->offset; in dmub_dcn35_setup_windows()
231 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); in dmub_dcn35_setup_windows()
233 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, in dmub_dcn35_setup_windows()
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| A D | dmub_dcn32.c | 216 const struct dmub_window *cw3, in dmub_dcn32_setup_windows() argument
224 offset = cw3->offset; in dmub_dcn32_setup_windows()
228 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); in dmub_dcn32_setup_windows()
230 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, in dmub_dcn32_setup_windows()
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| A D | dmub_dcn401.c | 199 const struct dmub_window *cw3, in dmub_dcn401_setup_windows() argument
207 offset = cw3->offset; in dmub_dcn401_setup_windows()
211 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); in dmub_dcn401_setup_windows()
213 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, in dmub_dcn401_setup_windows()
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| A D | dmub_srv.c | 660 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; in dmub_srv_hw_init() local
712 cw3.offset.quad_part = bios_fb->gpu_addr; in dmub_srv_hw_init()
713 cw3.region.base = DMUB_CW3_BASE; in dmub_srv_hw_init()
714 cw3.region.top = cw3.region.base + bios_fb->size; in dmub_srv_hw_init()
756 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); in dmub_srv_hw_init()
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| A D | dmub_dcn20.h | 197 const struct dmub_window *cw3,
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| A D | dmub_dcn31.h | 199 const struct dmub_window *cw3,
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| A D | dmub_dcn32.h | 206 const struct dmub_window *cw3,
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| A D | dmub_dcn35.h | 219 const struct dmub_window *cw3,
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| A D | dmub_dcn401.h | 216 const struct dmub_window *cw3,
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| /drivers/gpu/drm/amd/display/dmub/ |
| A D | dmub_srv.h | 420 const struct dmub_window *cw3,
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