| /drivers/gpu/drm/amd/display/dmub/src/ |
| A D | dmub_dcn30.c | 126 const struct dmub_window *cw5, in dmub_dcn30_setup_windows() argument
178 offset = cw5->offset; in dmub_dcn30_setup_windows()
182 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn30_setup_windows()
184 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn30_setup_windows()
191 cw5->region.top - cw5->region.base - 1, in dmub_dcn30_setup_windows()
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| A D | dmub_dcn20.c | 193 const struct dmub_window *cw5, in dmub_dcn20_setup_windows() argument
248 dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows()
252 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn20_setup_windows()
254 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn20_setup_windows()
261 cw5->region.top - cw5->region.base - 1, in dmub_dcn20_setup_windows()
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| A D | dmub_dcn31.c | 194 const struct dmub_window *cw5, in dmub_dcn31_setup_windows() argument
218 offset = cw5->offset; in dmub_dcn31_setup_windows()
222 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn31_setup_windows()
224 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn31_setup_windows()
231 cw5->region.top - cw5->region.base - 1, in dmub_dcn31_setup_windows()
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| A D | dmub_dcn35.c | 221 const struct dmub_window *cw5, in dmub_dcn35_setup_windows() argument
245 offset = cw5->offset; in dmub_dcn35_setup_windows()
249 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn35_setup_windows()
251 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn35_setup_windows()
258 cw5->region.top - cw5->region.base - 1, in dmub_dcn35_setup_windows()
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| A D | dmub_dcn32.c | 218 const struct dmub_window *cw5, in dmub_dcn32_setup_windows() argument
242 offset = cw5->offset; in dmub_dcn32_setup_windows()
246 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn32_setup_windows()
248 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn32_setup_windows()
255 cw5->region.top - cw5->region.base - 1, in dmub_dcn32_setup_windows()
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| A D | dmub_dcn401.c | 201 const struct dmub_window *cw5, in dmub_dcn401_setup_windows() argument
225 offset = cw5->offset; in dmub_dcn401_setup_windows()
229 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn401_setup_windows()
231 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn401_setup_windows()
238 cw5->region.top - cw5->region.base - 1, in dmub_dcn401_setup_windows()
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| A D | dmub_dcn30.h | 45 const struct dmub_window *cw5,
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| A D | dmub_srv.c | 660 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; in dmub_srv_hw_init() local
732 cw5.offset.quad_part = tracebuff_fb->gpu_addr; in dmub_srv_hw_init()
733 cw5.region.base = DMUB_CW5_BASE; in dmub_srv_hw_init()
734 cw5.region.top = cw5.region.base + tracebuff_fb->size; in dmub_srv_hw_init()
756 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); in dmub_srv_hw_init()
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| A D | dmub_dcn20.h | 199 const struct dmub_window *cw5,
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| A D | dmub_dcn31.h | 201 const struct dmub_window *cw5,
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| A D | dmub_dcn32.h | 208 const struct dmub_window *cw5,
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| A D | dmub_dcn35.h | 221 const struct dmub_window *cw5,
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| A D | dmub_dcn401.h | 218 const struct dmub_window *cw5,
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| /drivers/gpu/drm/amd/display/dmub/ |
| A D | dmub_srv.h | 422 const struct dmub_window *cw5,
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