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Searched refs:cycle (Results 1 – 25 of 62) sorted by relevance

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/drivers/staging/vme_user/
A Dvme_fake.c213 bridge->slaves[i].cycle = cycle; in fake_slave_set()
241 *cycle = bridge->slaves[i].cycle; in fake_slave_get()
321 bridge->masters[i].cycle = cycle; in fake_master_set()
352 *cycle = bridge->masters[i].cycle; in __fake_master_get()
429 if (cycle != bridge->slaves[i].cycle) in fake_vmeread8()
459 if (cycle != bridge->slaves[i].cycle) in fake_vmeread16()
492 if (cycle != bridge->slaves[i].cycle) in fake_vmeread32()
532 cycle = priv->masters[i].cycle; in fake_master_read()
622 if (cycle != bridge->slaves[i].cycle) in fake_vmewrite8()
721 cycle = bridge->masters[i].cycle; in fake_master_write()
[all …]
A Dvme_tsi148.c568 if (cycle & VME_BLT) in tsi148_slave_set()
650 *cycle = 0; in tsi148_slave_get()
683 *cycle |= VME_BLT; in tsi148_slave_get()
685 *cycle |= VME_MBLT; in tsi148_slave_get()
696 *cycle |= VME_USER; in tsi148_slave_get()
698 *cycle |= VME_PROG; in tsi148_slave_get()
700 *cycle |= VME_DATA; in tsi148_slave_get()
1074 *cycle = 0; in __tsi148_master_get()
1110 *cycle |= VME_SCT; in __tsi148_master_get()
1112 *cycle |= VME_BLT; in __tsi148_master_get()
[all …]
A Dvme_bridge.h50 u32 cycle; member
133 dma_addr_t *buf_base, u32 *aspace, u32 *cycle);
136 dma_addr_t buf_base, u32 aspace, u32 cycle);
141 u32 *aspace, u32 *cycle, u32 *dwidth);
144 u32 aspace, u32 cycle, u32 dwidth);
165 u32 aspace, u32 cycle);
167 u32 *aspace, u32 *cycle);
A Dvme.c137 u32 aspace, cycle, dwidth; in vme_get_size() local
252 u32 cycle) in vme_slave_request() argument
276 ((slave_image->cycle_attr & cycle) == cycle) && in vme_slave_request()
348 ((image->cycle_attr & cycle) == cycle))) { in vme_slave_set()
358 aspace, cycle); in vme_slave_set()
397 aspace, cycle); in vme_slave_get()
470 ((master_image->cycle_attr & cycle) == cycle) && in vme_master_request()
545 ((image->cycle_attr & cycle) == cycle) && in vme_master_set()
556 cycle, dwidth); in vme_master_set()
595 cycle, dwidth); in vme_master_get()
[all …]
A Dvme_user.h15 __u32 cycle; /* Cycle properties */ member
37 __u32 cycle; /* Cycle properties */ member
A Dvme_user.c333 &master.cycle, &master.dwidth); in vme_user_ioctl()
362 master.aspace, master.cycle, master.dwidth); in vme_user_ioctl()
378 &slave.aspace, &slave.cycle); in vme_user_ioctl()
403 slave.cycle); in vme_user_ioctl()
/drivers/ata/
A Dlibata-pata-timings.c70 q->cycle = EZ(t->cycle, T); in ata_timing_quantize()
92 m->cycle = max(a->cycle, b->cycle); in ata_timing_merge()
141 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; in ata_timing_compute()
144 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; in ata_timing_compute()
146 p.cycle = id[ATA_ID_EIDE_DMA_MIN]; in ata_timing_compute()
177 if (t->active + t->recover < t->cycle) { in ata_timing_compute()
178 t->active += (t->cycle - (t->active + t->recover)) / 2; in ata_timing_compute()
179 t->recover = t->cycle - t->active; in ata_timing_compute()
187 if (t->active + t->recover > t->cycle) in ata_timing_compute()
188 t->cycle = t->active + t->recover; in ata_timing_compute()
A Dpata_icside.c192 unsigned int cycle; in pata_icside_set_dmamode() local
205 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) { in pata_icside_set_dmamode()
207 cycle = 187; in pata_icside_set_dmamode()
208 } else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) { in pata_icside_set_dmamode()
210 cycle = 250; in pata_icside_set_dmamode()
211 } else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) { in pata_icside_set_dmamode()
213 cycle = 437; in pata_icside_set_dmamode()
216 cycle = 562; in pata_icside_set_dmamode()
220 t.active, t.recover, t.cycle, iomd_type); in pata_icside_set_dmamode()
222 state->port[ap->port_no].speed[adev->devno] = cycle; in pata_icside_set_dmamode()
A Dpata_acpi.c123 acpi->gtm.drive[unit].pio = t->cycle; in pacpi_set_piomode()
150 acpi->gtm.drive[unit].dma = t->cycle; in pacpi_set_dmamode()
/drivers/clocksource/
A Dtimer-atmel-pit.c43 u32 cycle; member
85 elapsed += PIT_PICNT(t) * data->cycle; in read_pit_clk()
95 pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN); in pit_clkevt_shutdown()
107 data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); in pit_clkevt_set_periodic()
109 (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN); in pit_clkevt_set_periodic()
132 (data->cycle - 1) | AT91_PIT_PITEN); in at91sam926x_pit_reset()
153 data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, in at91sam926x_pit_interrupt()
210 data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ); in at91sam926x_pit_dt_init()
211 WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0); in at91sam926x_pit_dt_init()
220 bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */; in at91sam926x_pit_dt_init()
/drivers/pwm/
A Dpwm-sl28cpld.c129 unsigned int cycle, prescaler; in sl28cpld_pwm_apply() local
152 cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle); in sl28cpld_pwm_apply()
153 cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)); in sl28cpld_pwm_apply()
163 if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) { in sl28cpld_pwm_apply()
166 cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1); in sl28cpld_pwm_apply()
181 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); in sl28cpld_pwm_apply()
191 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); in sl28cpld_pwm_apply()
/drivers/cxl/core/
A Dedac.c151 u8 cycle, u8 flags) in cxl_scrub_set_attrbs_region() argument
188 cycle); in cxl_scrub_set_attrbs_region()
190 cxlmd->scrub_cycle = cycle; in cxl_scrub_set_attrbs_region()
225 cycle); in cxl_scrub_set_attrbs_device()
227 cxlmd->scrub_cycle = cycle; in cxl_scrub_set_attrbs_device()
236 u8 cycle, u8 flags) in cxl_scrub_set_attrbs() argument
249 u16 cycle; in cxl_patrol_scrub_get_enabled_bg() local
287 u16 cycle; in cxl_patrol_scrub_get_min_scrub_cycle() local
312 u16 cycle; in cxl_patrol_scrub_get_scrub_cycle() local
372 u16 cycle; in cxl_memdev_scrub_init() local
[all …]
/drivers/mfd/
A Datmel-smc.c236 conf->cycle &= ~GENMASK(shift + 15, shift); in atmel_smc_cs_conf_set_cycle()
237 conf->cycle |= val << shift; in atmel_smc_cs_conf_set_cycle()
257 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle); in atmel_smc_cs_conf_apply()
278 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle); in atmel_hsmc_cs_conf_apply()
298 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle); in atmel_smc_cs_conf_get()
319 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle); in atmel_hsmc_cs_conf_get()
/drivers/net/ethernet/hisilicon/hns3/hns3pf/
A Dhclge_ptp.c13 ptp->cycle.quo = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG) & in hclge_ptp_get_cycle()
15 ptp->cycle.numer = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG); in hclge_ptp_get_cycle()
16 ptp->cycle.den = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); in hclge_ptp_get_cycle()
18 if (ptp->cycle.den == 0) { in hclge_ptp_get_cycle()
29 struct hclge_ptp_cycle *cycle = &hdev->ptp->cycle; in hclge_ptp_adjfine() local
34 adj_base = (u64)cycle->quo * (u64)cycle->den + (u64)cycle->numer; in hclge_ptp_adjfine()
42 quo = div_u64_rem(adj_val, cycle->den, &numerator); in hclge_ptp_adjfine()
48 writel(cycle->den, hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); in hclge_ptp_adjfine()
/drivers/net/dsa/sja1105/
A Dsja1105_tas.c174 int cycle = 0; in sja1105_init_scheduling() local
300 schedule_entry_points[cycle].subschindx = cycle; in sja1105_init_scheduling()
301 schedule_entry_points[cycle].delta = entry_point_delta; in sja1105_init_scheduling()
302 schedule_entry_points[cycle].address = schedule_start_idx; in sja1105_init_scheduling()
307 for (i = cycle; i < 8; i++) in sja1105_init_scheduling()
319 cycle++; in sja1105_init_scheduling()
336 schedule_entry_points[cycle].subschindx = cycle; in sja1105_init_scheduling()
337 schedule_entry_points[cycle].delta = entry_point_delta; in sja1105_init_scheduling()
338 schedule_entry_points[cycle].address = schedule_start_idx; in sja1105_init_scheduling()
340 for (i = cycle; i < 8; i++) in sja1105_init_scheduling()
/drivers/ptp/
A Dptp_kvm_common.c33 u64 cycle; in ptp_kvm_get_time_fn() local
39 ret = kvm_arch_ptp_get_crosststamp(&cycle, &tspec, &cs_id); in ptp_kvm_get_time_fn()
48 system_counter->cycles = cycle; in ptp_kvm_get_time_fn()
A Dptp_vmclock.c98 uint64_t cycle, delta, seq, frac_sec; in vmclock_get_crosststamp() local
138 cycle = systime_snapshot.cycles; in vmclock_get_crosststamp()
140 cycle = get_cycles(); in vmclock_get_crosststamp()
144 cycle = get_cycles(); in vmclock_get_crosststamp()
147 delta = cycle - le64_to_cpu(st->clk->counter_value); in vmclock_get_crosststamp()
172 system_counter->cycles = cycle; in vmclock_get_crosststamp()
A Dptp_kvm_x86.c95 int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *tspec, in kvm_arch_ptp_get_crosststamp() argument
123 *cycle = __pvclock_read_cycles(src, clock_pair->tsc); in kvm_arch_ptp_get_crosststamp()
/drivers/rtc/
A Drtc-fsl-ftm-alarm.c208 unsigned long long cycle; in ftm_rtc_set_alarm() local
214 cycle = (alm_time - ktime_get_real_seconds()) * rtc->alarm_freq; in ftm_rtc_set_alarm()
215 if (cycle > MAX_COUNT_VAL) { in ftm_rtc_set_alarm()
228 rtc_writel(rtc, FTM_MOD, cycle - 1); in ftm_rtc_set_alarm()
/drivers/firewire/
A Dcore-iso.c172 int cycle, int sync, int tags) in fw_iso_context_start() argument
174 trace_isoc_outbound_start(ctx, cycle); in fw_iso_context_start()
175 trace_isoc_inbound_single_start(ctx, cycle, sync, tags); in fw_iso_context_start()
176 trace_isoc_inbound_multiple_start(ctx, cycle, sync, tags); in fw_iso_context_start()
178 return ctx->card->driver->start_iso(ctx, cycle, sync, tags); in fw_iso_context_start()
/drivers/net/ethernet/intel/igc/
A Digc_tsn.c450 u32 sec, nsec, cycle; in igc_tsn_enable_offload() local
619 cycle = adapter->cycle_time; in igc_tsn_enable_offload()
627 s64 n = div64_s64(ktime_sub_ns(systim, base_time), cycle); in igc_tsn_enable_offload()
629 base_time = ktime_add_ns(base_time, (n + 1) * cycle); in igc_tsn_enable_offload()
654 wr32(IGC_QBVCYCLET_S, cycle); in igc_tsn_enable_offload()
655 wr32(IGC_QBVCYCLET, cycle); in igc_tsn_enable_offload()
/drivers/soc/aspeed/
A DKconfig8 tristate "ASPEED LPC firmware cycle control"
13 Control LPC firmware cycle mappings through ioctl()s. The driver
/drivers/net/ethernet/marvell/octeontx2/af/
A Dptp.c181 int cycle; in ptp_calc_adjusted_comp() local
200 cycle = cycles_per_sec - 1; in ptp_calc_adjusted_comp()
201 ptp_clock_nsec = (cycle * comp) >> 32; in ptp_calc_adjusted_comp()
205 cycle++; in ptp_calc_adjusted_comp()
206 ptp_clock_nsec = (cycle * comp) >> 32; in ptp_calc_adjusted_comp()
/drivers/perf/
A Dxgene_pmu.c280 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
281 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
298 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
299 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
315 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
325 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
378 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
421 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
464 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
477 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
[all …]
/drivers/mtd/chips/
A DKconfig132 flash chip addressed by each bus cycle, then say 'Y'.
139 flash chips addressed by each bus cycle, then say 'Y'.
146 flash chips addressed by each bus cycle, then say 'Y'.
153 flash chips addressed by each bus cycle, then say 'Y'.

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