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Searched refs:cycles (Results 1 – 25 of 138) sorted by relevance

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/drivers/memory/
A Djz4780-nemc.c162 uint32_t smcr, val, cycles; in jz4780_nemc_configure_bank() local
211 val, cycles); in jz4780_nemc_configure_bank()
215 smcr |= cycles << NEMC_SMCR_TAS_SHIFT; in jz4780_nemc_configure_bank()
223 val, cycles); in jz4780_nemc_configure_bank()
227 smcr |= cycles << NEMC_SMCR_TAH_SHIFT; in jz4780_nemc_configure_bank()
233 if (cycles > 31) { in jz4780_nemc_configure_bank()
235 val, cycles); in jz4780_nemc_configure_bank()
245 if (cycles > 31) { in jz4780_nemc_configure_bank()
247 val, cycles); in jz4780_nemc_configure_bank()
257 if (cycles > 63) { in jz4780_nemc_configure_bank()
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A Dbrcmstb_memc.c48 unsigned int cycles) in brcmstb_memc_srpd_config() argument
54 if (cycles > INACT_COUNT_MASK) in brcmstb_memc_srpd_config()
57 memc->timeout_cycles = cycles; in brcmstb_memc_srpd_config()
59 val = (cycles << INACT_COUNT_SHIFT) & INACT_COUNT_MASK; in brcmstb_memc_srpd_config()
60 if (cycles) in brcmstb_memc_srpd_config()
A Dpl172.c61 int cycles; in pl172_timing_prop() local
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
66 if (cycles < 0) { in pl172_timing_prop()
67 cycles = 0; in pl172_timing_prop()
68 } else if (cycles > max) { in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
/drivers/gpu/drm/i915/gt/
A Dselftest_gt_pm.c56 u32 cycles[5]; in measure_clocks() local
61 cycles[i] = -read_timestamp(engine); in measure_clocks()
66 cycles[i] += read_timestamp(engine); in measure_clocks()
72 sort(cycles, 5, sizeof(*cycles), cmp_u32, NULL); in measure_clocks()
73 *out_cycles = (cycles[1] + 2 * cycles[2] + cycles[3]) / 4; in measure_clocks()
99 u32 cycles; in live_gt_clocks() local
107 measure_clocks(engine, &cycles, &dt); in live_gt_clocks()
109 time = intel_gt_clock_interval_to_ns(engine->gt, cycles); in live_gt_clocks()
113 engine->name, cycles, time, dt, expected, in live_gt_clocks()
123 if (9 * expected < 8 * cycles || 8 * expected > 9 * cycles) { in live_gt_clocks()
A Dselftest_engine_cs.c148 u32 cycles[COUNT]; in perf_mi_bb_start() local
170 for (i = 0; i < ARRAY_SIZE(cycles); i++) { in perf_mi_bb_start()
203 cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2]; in perf_mi_bb_start()
211 engine->name, trifilter(cycles)); in perf_mi_bb_start()
276 u32 cycles[COUNT]; in perf_mi_noop() local
314 for (i = 0; i < ARRAY_SIZE(cycles); i++) { in perf_mi_noop()
358 cycles[i] = in perf_mi_noop()
369 engine->name, trifilter(cycles)); in perf_mi_noop()
/drivers/net/ethernet/mellanox/mlx4/
A Den_clock.c44 container_of(tc, struct mlx4_en_dev, cycles); in mlx4_en_read_clock()
139 mdev->cycles.mult = mult; in mlx4_en_phc_adjfine()
208 timecounter_init(&mdev->clock, &mdev->cycles, ns); in mlx4_en_phc_settime()
275 memset(&mdev->cycles, 0, sizeof(mdev->cycles)); in mlx4_en_init_timestamp()
276 mdev->cycles.read = mlx4_en_read_clock; in mlx4_en_init_timestamp()
277 mdev->cycles.mask = CLOCKSOURCE_MASK(48); in mlx4_en_init_timestamp()
278 mdev->cycles.shift = freq_to_shift(dev->caps.hca_core_clock); in mlx4_en_init_timestamp()
279 mdev->cycles.mult = in mlx4_en_init_timestamp()
280 clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift); in mlx4_en_init_timestamp()
281 mdev->nominal_c_mult = mdev->cycles.mult; in mlx4_en_init_timestamp()
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/drivers/net/wireless/ath/
A Dhw.c144 u32 cycles, busy, rx, tx; in ath_hw_cycle_counters_update() local
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
166 common->cc_ani.cycles += cycles; in ath_hw_cycle_counters_update()
171 common->cc_survey.cycles += cycles; in ath_hw_cycle_counters_update()
183 listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) / in ath_hw_get_listen_time()
/drivers/pwm/
A Dpwm-berlin.c81 u64 cycles; in berlin_pwm_config() local
83 cycles = clk_get_rate(bpc->clk); in berlin_pwm_config()
84 cycles *= period_ns; in berlin_pwm_config()
85 do_div(cycles, NSEC_PER_SEC); in berlin_pwm_config()
87 if (cycles > BERLIN_PWM_MAX_TCNT) { in berlin_pwm_config()
89 cycles >>= 12; // Prescaled by 4096 in berlin_pwm_config()
91 if (cycles > BERLIN_PWM_MAX_TCNT) in berlin_pwm_config()
95 period = cycles; in berlin_pwm_config()
96 cycles *= duty_ns; in berlin_pwm_config()
97 do_div(cycles, period_ns); in berlin_pwm_config()
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A Dpwm-xilinx.c35 u64 cycles) in xilinx_timer_tlr_cycles() argument
37 WARN_ON(cycles < 2 || cycles - 2 > priv->max); in xilinx_timer_tlr_cycles()
40 return cycles - 2; in xilinx_timer_tlr_cycles()
41 return priv->max - cycles + 2; in xilinx_timer_tlr_cycles()
47 u64 cycles; in xilinx_timer_get_period() local
50 cycles = tlr + 2; in xilinx_timer_get_period()
52 cycles = (u64)priv->max - tlr + 2; in xilinx_timer_get_period()
55 return DIV64_U64_ROUND_UP(cycles * NSEC_PER_SEC, in xilinx_timer_get_period()
A Dpwm-atmel.c186 unsigned long long cycles = state->period; in atmel_pwm_calculate_cprd_and_pres() local
190 cycles *= clkrate; in atmel_pwm_calculate_cprd_and_pres()
191 do_div(cycles, NSEC_PER_SEC); in atmel_pwm_calculate_cprd_and_pres()
198 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits; in atmel_pwm_calculate_cprd_and_pres()
205 cycles >>= *pres; in atmel_pwm_calculate_cprd_and_pres()
210 *cprd = cycles; in atmel_pwm_calculate_cprd_and_pres()
219 unsigned long long cycles = state->duty_cycle; in atmel_pwm_calculate_cdty() local
221 cycles *= clkrate; in atmel_pwm_calculate_cdty()
222 do_div(cycles, NSEC_PER_SEC); in atmel_pwm_calculate_cdty()
223 cycles >>= pres; in atmel_pwm_calculate_cdty()
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/drivers/char/hw_random/
A Dcavium-rng-vf.c85 u64 status, cycles; in check_rng_health() local
99 cycles = status >> 1; in check_rng_health()
100 if (!cycles) in check_rng_health()
109 cycles = cycles / 2; in check_rng_health()
110 cur_err = (cycles * 1000000000) / rng->clock_rate; /* In nanosec */ in check_rng_health()
/drivers/net/ethernet/mellanox/mlxsw/
A Dspectrum_ptp.c85 struct cyclecounter cycles; member
155 u64 cycles = (u64) nsec; in mlxsw_sp1_ptp_ns2cycles() local
157 cycles <<= tc->cc->shift; in mlxsw_sp1_ptp_ns2cycles()
158 cycles = div_u64(cycles, tc->cc->mult); in mlxsw_sp1_ptp_ns2cycles()
160 return cycles; in mlxsw_sp1_ptp_ns2cycles()
167 u64 next_sec, next_sec_in_nsec, cycles; in mlxsw_sp1_ptp_phc_settime() local
179 mlxsw_reg_mtpps_vpin_pack(mtpps_pl, cycles); in mlxsw_sp1_ptp_phc_settime()
224 u64 cycles, nsec; in mlxsw_sp1_ptp_gettimex() local
285 clock->cycles.read = mlxsw_sp1_ptp_read_frc; in mlxsw_sp1_ptp_clock_init()
288 clock->cycles.shift); in mlxsw_sp1_ptp_clock_init()
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/drivers/clocksource/
A Dexynos_mct.c274 static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles) in exynos4_mct_comp0_start() argument
283 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); in exynos4_mct_comp0_start()
286 comp_cycle = exynos4_read_count_64() + cycles; in exynos4_mct_comp0_start()
296 static int exynos4_comp_set_next_event(unsigned long cycles, in exynos4_comp_set_next_event() argument
299 exynos4_mct_comp0_start(false, cycles); in exynos4_comp_set_next_event()
374 static void exynos4_mct_tick_start(unsigned long cycles, in exynos4_mct_tick_start() argument
381 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ in exynos4_mct_tick_start()
402 static int exynos4_tick_set_next_event(unsigned long cycles, in exynos4_tick_set_next_event() argument
408 exynos4_mct_tick_start(cycles, mevt); in exynos4_tick_set_next_event()
A Dtimer-sprd.c60 static void sprd_timer_update_counter(void __iomem *base, unsigned long cycles) in sprd_timer_update_counter() argument
62 writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO); in sprd_timer_update_counter()
79 static int sprd_timer_set_next_event(unsigned long cycles, in sprd_timer_set_next_event() argument
85 sprd_timer_update_counter(timer_of_base(to), cycles); in sprd_timer_set_next_event()
A Dtimer-rda.c35 static int rda_ostimer_start(void __iomem *base, bool periodic, u64 cycles) in rda_ostimer_start() argument
39 load_l = (u32)cycles; in rda_ostimer_start()
40 ctrl = ((cycles >> 32) & 0xffffff); in rda_ostimer_start()
A Dtimer-rockchip.c65 static void rk_timer_update_counter(unsigned long cycles, in rk_timer_update_counter() argument
68 writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0); in rk_timer_update_counter()
77 static inline int rk_timer_set_next_event(unsigned long cycles, in rk_timer_set_next_event() argument
83 rk_timer_update_counter(cycles, timer); in rk_timer_set_next_event()
/drivers/net/ethernet/mellanox/mlx5/core/lib/
A Dclock.c280 .cycles = host, in mlx5_mtctr_syncdevicetime()
370 clock_info->cycles = timer->tc.cycle_last; in mlx5_update_clock_info_page()
371 clock_info->mult = timer->cycles.mult; in mlx5_update_clock_info_page()
499 u64 cycles, ns; in mlx5_ptp_gettimex() local
508 cycles = mlx5_read_time(mdev, sts, false); in mlx5_ptp_gettimex()
622 timer->cycles.mult = mult; in mlx5_ptp_adjfine()
714 timer->cycles.mult); in find_target_cycles()
1145 timer->cycles.shift); in mlx5_timecounter_init()
1203 info->cycles = timer->tc.cycle_last; in mlx5_init_clock_info()
1204 info->mask = timer->cycles.mask; in mlx5_init_clock_info()
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/drivers/siox/
A Dsiox-bus-gpio.c34 size_t cycles = max(setbuf_len, getbuf_len); in siox_gpio_pushpull() local
44 for (i = 0; i < cycles; ++i) { in siox_gpio_pushpull()
48 if (i >= cycles - setbuf_len) in siox_gpio_pushpull()
49 set = setbuf[i - (cycles - setbuf_len)]; in siox_gpio_pushpull()
/drivers/net/ethernet/broadcom/bnxt/
A Dbnxt_ptp.h190 u64 time, cycles; in bnxt_extend_cycles_32b_to_48b() local
193 cycles = (time & BNXT_HI_TIMER_MASK) | ts; in bnxt_extend_cycles_32b_to_48b()
195 cycles += BNXT_LO_TIMER_MASK + 1; in bnxt_extend_cycles_32b_to_48b()
196 return cycles; in bnxt_extend_cycles_32b_to_48b()
/drivers/soc/ixp4xx/
A Dixp4xx-npe.c415 int cycles = 0; in npe_send_message() local
434 while ((cycles < MAX_RETRIES) && in npe_send_message()
437 cycles++; in npe_send_message()
440 if (cycles == MAX_RETRIES) { in npe_send_message()
446 debug_msg(npe, "Sending a message took %i cycles\n", cycles); in npe_send_message()
454 int cycles = 0, cnt = 0; in npe_recv_message() local
458 while (cycles < MAX_RETRIES) { in npe_recv_message()
465 cycles++; in npe_recv_message()
478 if (cycles == MAX_RETRIES) { in npe_recv_message()
484 debug_msg(npe, "Receiving a message took %i cycles\n", cycles); in npe_recv_message()
/drivers/gpu/drm/bridge/
A Dnwl-dsi.c214 u32 cycles; in nwl_dsi_config_host() local
232 cycles = ui2bc(cfg->clk_pre); in nwl_dsi_config_host()
233 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles); in nwl_dsi_config_host()
234 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles); in nwl_dsi_config_host()
237 cycles += ui2bc(cfg->clk_pre); in nwl_dsi_config_host()
238 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles); in nwl_dsi_config_host()
239 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles); in nwl_dsi_config_host()
240 cycles = ps2bc(dsi, cfg->hs_exit); in nwl_dsi_config_host()
242 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles); in nwl_dsi_config_host()
249 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup); in nwl_dsi_config_host()
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/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
A Dfan.c129 u32 cycles, cur, prev; in nvkm_therm_fan_sense() local
145 cycles = 0; in nvkm_therm_fan_sense()
154 cycles++; in nvkm_therm_fan_sense()
157 } while (cycles < 5 && nvkm_timer_read(tmr) - start < 250000000); in nvkm_therm_fan_sense()
160 if (cycles == 5) { in nvkm_therm_fan_sense()
/drivers/gpu/drm/i915/selftests/
A Di915_request.c2019 u32 elapsed[TF_COUNT], cycles; in measure_semaphore_response() local
2078 cycles = trifilter(elapsed); in measure_semaphore_response()
2094 u32 elapsed[TF_COUNT], cycles; in measure_idle_dispatch() local
2149 cycles = trifilter(elapsed); in measure_idle_dispatch()
2226 cycles = trifilter(elapsed); in measure_busy_dispatch()
2339 cycles = trifilter(elapsed); in measure_inter_request()
2434 cycles = trifilter(elapsed); in measure_context_switch()
2453 u32 elapsed[TF_COUNT], cycles; in measure_preemption() local
2537 cycles = trifilter(elapsed); in measure_preemption()
2545 cycles = trifilter(elapsed); in measure_preemption()
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/drivers/media/usb/gspca/stv06xx/
A Dstv06xx_hdcs.c176 int cycles, err; in hdcs_set_exposure() local
179 cycles = val * HDCS_CLK_FREQ_MHZ * 257; in hdcs_set_exposure()
187 rowexp = cycles / rp; in hdcs_set_exposure()
190 cycles -= rowexp * rp; in hdcs_set_exposure()
195 srowexp = hdcs->w - (cycles + hdcs->exp.er + 13) / ct; in hdcs_set_exposure()
201 srowexp = cp - hdcs->exp.er - 6 - cycles; in hdcs_set_exposure()
/drivers/net/ethernet/intel/e1000e/
A Dptp.c127 system->cycles = sys_cycles; in e1000e_phc_get_syncdevicetime()
169 u64 cycles, ns; in e1000e_phc_gettimex() local
174 cycles = e1000e_read_systim(adapter, sts); in e1000e_phc_gettimex()
175 ns = timecounter_cyc2time(&adapter->tc, cycles); in e1000e_phc_gettimex()

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