Searched refs:d9 (Results 1 – 4 of 4) sorted by relevance
| /drivers/media/dvb-frontends/ |
| A D | dib9000.c | 99 } d9; member
1005 dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives); in dib9000_fw_reset()
1085 …if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.m… in dib9000_fw_init()
1090 f = &state->chip.d9.cfg.gpio_function[i]; in dib9000_fw_init()
1111 for (i = 0; i < state->chip.d9.cfg.subband.size; i++) { in dib9000_fw_init()
1112 b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz; in dib9000_fw_init()
1128 b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff); in dib9000_fw_init()
1131 b[29] = state->chip.d9.cfg.if_drives; in dib9000_fw_init()
1575 if (state->chip.d9.cfg.output_mpeg2_in_188_bytes) in dib9000_fw_set_output_mode()
2512 …if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMO… in dib9000_attach()
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| /drivers/ipack/devices/ |
| A D | scc2698.h | 57 u8 d9, srb; /* Status register (b) */ member
75 u8 d9, csrb; /* Clock select register (a) */ member
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| /drivers/tty/vt/ |
| A D | cp437.uni | 26 0x0a U+25d9
105 0x55 U+0055 U+00d9 U+00da U+00db
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| /drivers/media/v4l2-core/ |
| A D | v4l2-vp9.c | 1110 #define DIVS_INV(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9) \ in fastdiv() argument
1113 DIV_INV(d8), DIV_INV(d9) in fastdiv()
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