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Searched refs:dcc (Results 1 – 25 of 51) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
A Ddcn30_hubp.c367 struct dc_plane_dcc_param *dcc) in hubp3_dcc_control_sienna_cichlid() argument
372 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
373 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
374 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c, in hubp3_dcc_control_sienna_cichlid()
375 SECONDARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
376 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
377 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c); in hubp3_dcc_control_sienna_cichlid()
417 struct dc_plane_dcc_param *dcc, in hubp3_program_surface_config() argument
423 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp3_program_surface_config()
425 hubp2_program_size(hubp, format, plane_size, dcc); in hubp3_program_surface_config()
A Ddcn30_hubp.h270 struct dc_plane_dcc_param *dcc,
290 struct dc_plane_dcc_param *dcc);
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_plane.c266 const struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_validate_dcc() argument
277 if (!dcc->enable) in amdgpu_dm_plane_validate_dcc()
303 if (dcc->independent_64b_blks == 0 && in amdgpu_dm_plane_validate_dcc()
331 dcc->enable = 1; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
332 dcc->meta_pitch = afb->base.pitches[1]; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
382 dcc->enable = 1; in amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers()
386 dcc->dcc_ind_blk = hubp_ind_block_64b; in amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers()
845 struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_fill_plane_buffer_attributes() argument
854 memset(dcc, 0, sizeof(*dcc)); in amdgpu_dm_plane_fill_plane_buffer_attributes()
906 tiling_info, dcc, in amdgpu_dm_plane_fill_plane_buffer_attributes()
[all …]
A Damdgpu_dm_plane.h52 struct dc_plane_dcc_param *dcc,
/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
A Ddcn201_hubp.c48 struct dc_plane_dcc_param *dcc, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
/drivers/bus/
A Dvexpress-config.c108 u32 *position, u32 *dcc) in vexpress_config_get_topo() argument
116 vexpress_config_find_prop(node, "arm,vexpress,dcc", dcc); in vexpress_config_get_topo()
257 u32 site, position, dcc; in vexpress_syscfg_regmap_init() local
261 &position, &dcc); in vexpress_syscfg_regmap_init()
301 func, site, position, dcc, in vexpress_syscfg_regmap_init()
304 func->template[i] = SYS_CFGCTRL_DCC(dcc); in vexpress_syscfg_regmap_init()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c724 surface->dcc.enable = false; in populate_dml21_dummy_surface_cfg()
725 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_dummy_surface_cfg()
726 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_dummy_surface_cfg()
727 surface->dcc.informative.fraction_of_zero_size_request_plane0 = 0; in populate_dml21_dummy_surface_cfg()
790 surface->dcc.enable = plane_state->dcc.enable; in populate_dml21_surface_config_from_plane_state()
791 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_surface_config_from_plane_state()
792 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_surface_config_from_plane_state()
793 …surface->dcc.informative.fraction_of_zero_size_request_plane0 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
794 …surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
795 surface->dcc.plane0.pitch = plane_state->dcc.meta_pitch; in populate_dml21_surface_config_from_plane_state()
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A Ddml21_utils.c305 memcpy(&phantom_plane->dcc, &main_plane->dcc, sizeof(phantom_plane->dcc)); in dml21_add_phantom_plane()
/drivers/gpu/drm/amd/display/dc/hubp/dcn35/
A Ddcn35_hubp.c178 struct dc_plane_dcc_param *dcc, in hubp35_program_surface_config() argument
184 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp35_program_surface_config()
186 hubp2_program_size(hubp, format, plane_size, dcc); in hubp35_program_surface_config()
A Ddcn35_hubp.h71 struct dc_plane_dcc_param *dcc,
/drivers/usb/typec/ucsi/
A Ducsi_huawei_gaokun.c215 u8 dcc, ddi; in gaokun_ucsi_port_update() local
217 dcc = port_data[offset]; in gaokun_ucsi_port_update()
222 port->ccx = FIELD_GET(GAOKUN_CCX_MASK, dcc); in gaokun_ucsi_port_update()
223 port->mux = FIELD_GET(GAOKUN_MUX_MASK, dcc); in gaokun_ucsi_port_update()
/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.c167 struct dc_plane_dcc_param *dcc) in hubp1_program_size() argument
180 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
182 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp1_program_size()
185 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
190 if (!dcc->enable) { in hubp1_program_size()
561 struct dc_plane_dcc_param *dcc, in hubp1_program_surface_config() argument
565 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp1_program_surface_config()
567 hubp1_program_size(hubp, format, plane_size, dcc); in hubp1_program_surface_config()
/drivers/gpu/drm/i915/gt/
A Dintel_ggtt_fencing.c669 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle() local
680 switch (dcc & DCC_ADDRESSING_MODE_MASK) { in detect_bit_6_swizzle()
687 if (dcc & DCC_CHANNEL_XOR_DISABLE) { in detect_bit_6_swizzle()
694 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { in detect_bit_6_swizzle()
713 if (dcc == 0xffffffff) { in detect_bit_6_swizzle()
/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.c536 struct dc_plane_dcc_param *dcc) in hubp401_dcc_control() argument
541 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp401_dcc_control()
542 SECONDARY_SURFACE_DCC_EN, dcc->enable); in hubp401_dcc_control()
562 struct dc_plane_dcc_param *dcc) in hubp401_program_size() argument
598 struct dc_plane_dcc_param *dcc, in hubp401_program_surface_config() argument
604 hubp401_dcc_control(hubp, dcc); in hubp401_program_surface_config()
606 hubp401_program_size(hubp, format, plane_size, dcc); in hubp401_program_surface_config()
A Ddcn401_hubp.h275 struct dc_plane_dcc_param *dcc);
286 struct dc_plane_dcc_param *dcc);
294 struct dc_plane_dcc_param *dcc,
/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
A Ddcn20_hubp.c332 struct dc_plane_dcc_param *dcc) in hubp2_program_size() argument
350 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
352 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp2_program_size()
355 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
360 if (!dcc->enable) { in hubp2_program_size()
556 struct dc_plane_dcc_param *dcc, in hubp2_program_surface_config() argument
562 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp2_program_surface_config()
564 hubp2_program_size(hubp, format, plane_size, dcc); in hubp2_program_surface_config()
A Ddcn20_hubp.h370 struct dc_plane_dcc_param *dcc);
387 struct dc_plane_dcc_param *dcc,
/drivers/s390/cio/
A Dqdio_main.c726 int dstat, int dcc) in qdio_establish_handle_irq() argument
734 if (dcc == 1) in qdio_establish_handle_irq()
754 int cstat, dstat, rc, dcc; in qdio_int_handler() local
774 dcc = scsw_cmd_is_valid_cc(&irb->scsw) ? irb->scsw.cmd.cc : 0; in qdio_int_handler()
779 rc = qdio_establish_handle_irq(irq_ptr, cstat, dstat, dcc); in qdio_int_handler()
793 else if (dcc == 1) in qdio_int_handler()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_mall_phantom.c86 if (pipe->plane_state->dcc.enable) in dml2_helper_calculate_num_ways_for_subvp()
767 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); in enable_phantom_plane()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dmem_input.h170 struct dc_plane_dcc_param *dcc,
A Dhubp.h198 struct dc_plane_dcc_param *dcc,
/drivers/tty/hvc/
A Dhvc_dcc.c63 EARLYCON_DECLARE(dcc, dcc_early_console_setup);
/drivers/gpu/drm/amd/display/dc/
A Ddc_dmub_srv.h253 uint32_t dcc : 1; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_display_cfg_types.h196 } dcc; member
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c323 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
337 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch; in pipe_ctx_to_e2e_pipe_params()
993 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; in dcn_validate_bandwidth()

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