Home
last modified time | relevance | path

Searched refs:dce (Results 1 – 24 of 24) sorted by relevance

/drivers/gpu/drm/amd/display/dc/resource/dce112/
A Ddce112_resource.c903 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
911 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
912 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
928 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
929 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
944 context->bw_ctx.bw.dce.stutter_mode_enable, in dce112_validate_bandwidth()
948 context->bw_ctx.bw.dce.all_displays_in_sync, in dce112_validate_bandwidth()
949 context->bw_ctx.bw.dce.dispclk_khz, in dce112_validate_bandwidth()
950 context->bw_ctx.bw.dce.sclk_khz, in dce112_validate_bandwidth()
951 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce112_validate_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
/drivers/gpu/drm/amd/display/dc/resource/dce110/
A Ddce110_resource.c980 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
990 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
991 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1007 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1008 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1023 context->bw_ctx.bw.dce.stutter_mode_enable, in dce110_validate_bandwidth()
1027 context->bw_ctx.bw.dce.all_displays_in_sync, in dce110_validate_bandwidth()
1028 context->bw_ctx.bw.dce.dispclk_khz, in dce110_validate_bandwidth()
1029 context->bw_ctx.bw.dce.sclk_khz, in dce110_validate_bandwidth()
1030 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce110_validate_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clk_mgr.c227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
634 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
647 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
678 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
705 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
732 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
[all …]
A DMakefile35 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
/drivers/net/wan/
A Dhdlc_fr.c352 if (state(hdlc)->settings.dce) { in pvc_close()
462 int dce = state(hdlc)->settings.dce; in fr_lmi_send() local
468 if (dce && fullrep) { in fr_lmi_send()
502 if (dce && fullrep) { in fr_lmi_send()
590 if (state(hdlc)->settings.dce) { in fr_timer()
615 if (state(hdlc)->settings.dce) { in fr_timer()
639 int dce = state(hdlc)->settings.dce; in fr_lmi_recv() local
716 if (dce) in fr_lmi_recv()
728 if (dce) { in fr_lmi_recv()
1229 (new_settings.dce != 0 && in fr_ioctl()
[all …]
A Dhdlc_x25.c202 if (state(hdlc)->settings.dce) in x25_open()
307 new_settings.dce = 0; in x25_ioctl()
317 if ((new_settings.dce != 0 && in x25_ioctl()
318 new_settings.dce != 1) || in x25_ioctl()
/drivers/gpu/drm/amd/display/dc/bios/
A Dcommand_table_helper2.c37 enum dce_version dce) in dal_bios_parser_init_cmd_tbl_helper2() argument
39 switch (dce) { in dal_bios_parser_init_cmd_tbl_helper2()
A Dcommand_table_helper.c36 enum dce_version dce) in dal_bios_parser_init_cmd_tbl_helper() argument
38 switch (dce) { in dal_bios_parser_init_cmd_tbl_helper()
A Dcommand_table_helper2.h38 enum dce_version dce);
A Dcommand_table_helper.h38 enum dce_version dce);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
A Ddce_clk_mgr.c208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
408 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
/drivers/gpu/drm/amd/display/dc/
A DMakefile25 DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc dpp hubbub dccg …
/drivers/gpu/drm/amd/display/dc/resource/dce100/
A Ddce100_resource.c854 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce100_validate_bandwidth()
855 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; in dce100_validate_bandwidth()
857 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce100_validate_bandwidth()
858 context->bw_ctx.bw.dce.yclk_khz = 0; in dce100_validate_bandwidth()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
A Ddce120_clk_mgr.c91 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
A Ddce60_clk_mgr.c126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
/drivers/gpu/drm/amd/display/dc/hwss/
A DMakefile50 AMD_DAL_HWSS_DCE = $(addprefix $(AMDDALPATH)/dc/hwss/dce/,$(HWSS_DCE))
/drivers/gpu/drm/amd/display/dc/resource/dce60/
A Ddce60_resource.c881 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce60_validate_bandwidth()
882 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; in dce60_validate_bandwidth()
884 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce60_validate_bandwidth()
885 context->bw_ctx.bw.dce.yclk_khz = 0; in dce60_validate_bandwidth()
/drivers/gpu/drm/amd/display/dc/resource/dce80/
A Ddce80_resource.c887 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce80_validate_bandwidth()
888 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; in dce80_validate_bandwidth()
890 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce80_validate_bandwidth()
891 context->bw_ctx.bw.dce.yclk_khz = 0; in dce80_validate_bandwidth()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
A Ddce112_clk_mgr.c197 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c2058 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], in dce110_set_displaymarks()
2059 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], in dce110_set_displaymarks()
2060 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], in dce110_set_displaymarks()
2061 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], in dce110_set_displaymarks()
2067 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], in dce110_set_displaymarks()
2068 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], in dce110_set_displaymarks()
2069 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], in dce110_set_displaymarks()
/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h576 struct dce_bw_output dce; member
/drivers/gpu/drm/amd/display/dc/core/
A Ddc.c2278 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_commit_state_no_check()
2524 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_post_update_surfaces_to_stream()
5210 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in update_planes_and_stream_v1()
/drivers/scsi/
A Dscsi_debug.c2942 unsigned char dce) in resp_compression_m_pg() argument
2950 if (dce) in resp_compression_m_pg()

Completed in 65 milliseconds