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Searched refs:dclk (Results 1 – 25 of 87) sorted by relevance

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/drivers/gpu/drm/sun4i/
A Dsun4i_tcon_dclk.c74 struct sun4i_tcon *tcon = dclk->tcon; in sun4i_dclk_round_rate()
169 struct sun4i_dclk *dclk; in sun4i_dclk_create() local
179 dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL); in sun4i_dclk_create()
180 if (!dclk) in sun4i_dclk_create()
182 dclk->tcon = tcon; in sun4i_dclk_create()
190 dclk->regmap = tcon->regs; in sun4i_dclk_create()
191 dclk->hw.init = &init; in sun4i_dclk_create()
193 tcon->dclk = clk_register(dev, &dclk->hw); in sun4i_dclk_create()
194 if (IS_ERR(tcon->dclk)) in sun4i_dclk_create()
195 return PTR_ERR(tcon->dclk); in sun4i_dclk_create()
[all …]
/drivers/clk/hisilicon/
A Dclkdivider-hi6220.c51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
76 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in hi6220_clkdiv_set_rate()
78 if (dclk->lock) in hi6220_clkdiv_set_rate()
79 spin_lock_irqsave(dclk->lock, flags); in hi6220_clkdiv_set_rate()
81 data = readl_relaxed(dclk->reg); in hi6220_clkdiv_set_rate()
82 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate()
83 data |= value << dclk->shift; in hi6220_clkdiv_set_rate()
84 data |= dclk->mask; in hi6220_clkdiv_set_rate()
86 writel_relaxed(data, dclk->reg); in hi6220_clkdiv_set_rate()
[all …]
/drivers/clk/nuvoton/
A Dclk-ma35d1-divider.c35 val = readl_relaxed(dclk->reg) >> dclk->shift; in ma35d1_clkdiv_recalc_rate()
36 val &= clk_div_mask(dclk->width); in ma35d1_clkdiv_recalc_rate()
47 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_round_rate()
58 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_set_rate()
60 spin_lock_irqsave(dclk->lock, flags); in ma35d1_clkdiv_set_rate()
62 data = readl_relaxed(dclk->reg); in ma35d1_clkdiv_set_rate()
63 data &= ~(clk_div_mask(dclk->width) << dclk->shift); in ma35d1_clkdiv_set_rate()
64 data |= (value - 1) << dclk->shift; in ma35d1_clkdiv_set_rate()
65 data |= dclk->mask; in ma35d1_clkdiv_set_rate()
66 writel_relaxed(data, dclk->reg); in ma35d1_clkdiv_set_rate()
[all …]
/drivers/siox/
A Dsiox-bus-gpio.c20 struct gpio_desc *dclk; member
38 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
60 gpiod_set_value_cansleep(ddata->dclk, 1); in siox_gpio_pushpull()
62 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
112 ddata->dclk = devm_gpiod_get(dev, "dclk", GPIOD_OUT_LOW); in siox_gpio_probe()
113 if (IS_ERR(ddata->dclk)) in siox_gpio_probe()
114 return dev_err_probe(dev, PTR_ERR(ddata->dclk), in siox_gpio_probe()
/drivers/clk/
A Dclk-lmk04832.c267 struct lmk_dclk *dclk; member
1014 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_is_enabled()
1029 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_prepare()
1039 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_unprepare()
1050 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_recalc_rate()
1076 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_round_rate()
1098 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_set_rate()
1311 lmk->dclk[dclk_num].id = num; in lmk04832_register_clkout()
1312 lmk->dclk[dclk_num].lmk = lmk; in lmk04832_register_clkout()
1313 lmk->dclk[dclk_num].hw.init = &init; in lmk04832_register_clkout()
[all …]
/drivers/video/fbdev/riva/
A Dnv_driver.c276 unsigned long dclk = 0; in riva_get_maxdclk() local
286 dclk = 800000; in riva_get_maxdclk()
288 dclk = 1000000; in riva_get_maxdclk()
294 dclk = 1000000; in riva_get_maxdclk()
303 dclk = 800000; in riva_get_maxdclk()
306 dclk = 1000000; in riva_get_maxdclk()
311 return dclk; in riva_get_maxdclk()
/drivers/gpu/drm/i915/display/
A Dintel_bw.c61 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; member
99 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
101 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
122 u16 dclk; in icl_pcode_read_qgv_point_info() local
131 dclk = val & 0xffff; in icl_pcode_read_qgv_point_info()
132 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
224 u16 dclk; in mtl_read_qgv_point_info() local
231 sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); in mtl_read_qgv_point_info()
381 u16 dclk = 0; in icl_sagv_max_dclk() local
385 dclk = max(dclk, qi->points[i].dclk); in icl_sagv_max_dclk()
[all …]
/drivers/gpu/drm/renesas/rz-du/
A Drzg2l_du_crtc.c71 clk_prepare_enable(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_set_display_timing()
72 clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock); in rzg2l_du_crtc_set_display_timing()
209 clk_disable_unprepare(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_put()
401 rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk"); in rzg2l_du_crtc_create()
402 if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) { in rzg2l_du_crtc_create()
404 return PTR_ERR(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_create()
A Drzg2l_du_crtc.h61 struct clk *dclk; member
/drivers/video/fbdev/core/
A Dfbmon.c1019 u32 dclk; member
1111 dclk /= 1000; in fb_get_hblank_by_dclk()
1114 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk); in fb_get_hblank_by_dclk()
1158 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1169 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
1177 timings->hfreq = timings->dclk/timings->htotal; in fb_timings_dclk()
1269 if (timings->dclk > dclkmax) { in fb_get_mode()
1270 timings->dclk = dclkmax; in fb_get_mode()
1283 timings->dclk = PICOS2KHZ(val) * 1000; in fb_get_mode()
1294 timings->dclk < dclkmin || timings->dclk > dclkmax))) { in fb_get_mode()
[all …]
/drivers/gpu/drm/radeon/
A Drs780_dpm.c571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
A Dtrinity_dpm.c850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
863 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal()
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1411 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index()
1645 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info()
1648 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1890 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table()
1973 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1998 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
A Dsumo_dpm.c822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
839 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_before_set_eng_clock()
857 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_after_set_eng_clock()
1413 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in sumo_parse_pplib_non_clock_info()
1416 rps->dclk = 0; in sumo_parse_pplib_non_clock_info()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
A Drv770_dpm.c1441 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1458 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2156 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rv7xx_parse_pplib_non_clock_info()
2159 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2165 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2442 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2486 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
A Drv6xx_dpm.c1519 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
A Dradeon_uvd.c949 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
964 vco_min = max3(vco_min, vclk, dclk); in radeon_uvd_calc_upll_dividers()
985 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, in radeon_uvd_calc_upll_dividers()
991 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
A Dtrinity_dpm.h69 u32 dclk; member
A Dradeon_asic.h409 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
476 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
533 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
534 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
748 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
786 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
/drivers/gpu/drm/rockchip/
A Drockchip_drm_vop.c177 struct clk *dclk; member
634 ret = clk_enable(vop->dclk); in vop_enable()
702 clk_disable(vop->dclk); in vop_enable()
774 clk_disable(vop->dclk); in vop_crtc_atomic_disable()
1244 rate = clk_round_rate(vop->dclk, in vop_crtc_mode_fixup()
2016 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); in vop_initial()
2017 if (IS_ERR(vop->dclk)) { in vop_initial()
2019 return PTR_ERR(vop->dclk); in vop_initial()
2028 ret = clk_prepare(vop->dclk); in vop_initial()
2108 clk_unprepare(vop->dclk); in vop_initial()
[all …]
A Drockchip_drm_vop2.c972 clk_set_parent(vp->dclk, vp->dclk_src); in vop2_crtc_atomic_disable()
974 clk_disable_unprepare(vp->dclk); in vop2_crtc_atomic_disable()
1638 ret = clk_prepare_enable(vp->dclk); in vop2_crtc_atomic_enable()
1749 vp->dclk_src = clk_get_parent(vp->dclk); in vop2_crtc_atomic_enable()
1751 ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); in vop2_crtc_atomic_enable()
1763 vp->dclk_src = clk_get_parent(vp->dclk); in vop2_crtc_atomic_enable()
1765 ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); in vop2_crtc_atomic_enable()
1774 clk_set_rate(vp->dclk, clock); in vop2_crtc_atomic_enable()
2357 vp->dclk = devm_clk_get(vop2->dev, dclk_name); in vop2_create_crtcs()
2358 if (IS_ERR(vp->dclk)) in vop2_create_crtcs()
[all …]
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dhwmgr_ppt.h59 uint32_t dclk; /* UVD D-clock */ member
/drivers/gpu/drm/amd/pm/powerplay/inc/
A Dpower_state.h185 unsigned long dclk; member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Ddcn301_smu.h39 uint32_t dclk; member
/drivers/gpu/drm/amd/amdgpu/
A Dsi.c1729 unsigned vclk, unsigned dclk, in si_calc_upll_dividers() argument
1744 vco_min = max(max(vco_min, vclk), dclk); in si_calc_upll_dividers()
1764 dclk_div = si_uvd_calc_upll_post_div(vco_freq, dclk, in si_calc_upll_dividers()
1770 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1790 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in si_set_uvd_clocks() argument
1803 if (!vclk || !dclk) { in si_set_uvd_clocks()
1808 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000, in si_set_uvd_clocks()
/drivers/video/fbdev/
A Dssd1307fb.c339 u32 precharge, dclk, com_invdir, compins; in ssd1307fb_init() local
404 dclk = ((par->dclk_div - 1) & 0xf) | (par->dclk_frq & 0xf) << 4; in ssd1307fb_init()
405 ret = ssd1307fb_write_cmd(par->client, dclk); in ssd1307fb_init()

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