| /drivers/video/fbdev/geode/ |
| A D | display_gx1.c | 80 u32 gcfg, tcfg, ocfg, dclk_div, val; in gx1_set_mode() local
108 dclk_div = DC_GCFG_DCLK_DIV_1; /* FIXME: may need to divide DCLK by 2 sometimes? */ in gx1_set_mode()
109 gcfg |= dclk_div; in gx1_set_mode()
122 gcfg = DC_GCFG_VRDY | dclk_div; in gx1_set_mode()
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| /drivers/clk/ |
| A D | clk-lmk04832.c | 1051 unsigned int dclk_div; in lmk04832_dclk_recalc_rate() local
1067 rate = DIV_ROUND_CLOSEST(prate, dclk_div); in lmk04832_dclk_recalc_rate()
1078 unsigned int dclk_div; in lmk04832_dclk_round_rate() local
1083 if (dclk_div < 1 || dclk_div > 0x3ff) { in lmk04832_dclk_round_rate()
1099 unsigned int dclk_div; in lmk04832_dclk_set_rate() local
1102 dclk_div = DIV_ROUND_CLOSEST(prate, rate); in lmk04832_dclk_set_rate()
1104 if (dclk_div > 0x3ff) { in lmk04832_dclk_set_rate()
1110 if (dclk_div == 1) { in lmk04832_dclk_set_rate()
1124 if (dclk_div == 2 || dclk_div == 3) { in lmk04832_dclk_set_rate()
1138 FIELD_GET(0x0ff, dclk_div)); in lmk04832_dclk_set_rate()
[all …]
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| /drivers/gpu/drm/radeon/ |
| A D | radeon_uvd.c | 968 unsigned vclk_div, dclk_div, score; in radeon_uvd_calc_upll_dividers() local
985 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, in radeon_uvd_calc_upll_dividers()
987 if (dclk_div > pd_max) in radeon_uvd_calc_upll_dividers()
991 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
997 *optimal_dclk_div = dclk_div; in radeon_uvd_calc_upll_dividers()
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| A D | rv770.c | 56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
76 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
82 dclk_div -= 1; in rv770_set_uvd_clocks()
106 UPLL_SW_HILEN2(dclk_div >> 1) | in rv770_set_uvd_clocks()
107 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)), in rv770_set_uvd_clocks()
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| A D | r600.c | 205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
234 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
263 UPLL_SW_HILEN2(dclk_div >> 1) | in r600_set_uvd_clocks()
264 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | in r600_set_uvd_clocks()
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| A D | evergreen.c | 1192 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1211 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1250 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in evergreen_set_uvd_clocks()
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| A D | si.c | 6977 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
6995 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7036 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()
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| /drivers/video/fbdev/ |
| A D | ssd1307fb.c | 69 u32 dclk_div; member
404 dclk = ((par->dclk_div - 1) & 0xf) | (par->dclk_frq & 0xf) << 4; in ssd1307fb_init()
663 if (device_property_read_u32(dev, "solomon,dclk-div", &par->dclk_div)) in ssd1307fb_probe()
664 par->dclk_div = par->device_info->default_dclk_div; in ssd1307fb_probe()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | si.c | 1747 unsigned vclk_div, dclk_div, score; in si_calc_upll_dividers() local
1764 dclk_div = si_uvd_calc_upll_post_div(vco_freq, dclk, in si_calc_upll_dividers()
1766 if (dclk_div > pd_max) in si_calc_upll_dividers()
1770 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1776 *optimal_dclk_div = dclk_div; in si_calc_upll_dividers()
1792 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
1810 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
1853 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()
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| /drivers/gpu/drm/solomon/ |
| A D | ssd130x.h | 85 u32 dclk_div; member
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| A D | ssd130x.c | 440 dclk = (SSD130X_SET_CLOCK_DIV_SET(ssd130x->dclk_div - 1) | in ssd130x_init()
1859 if (device_property_read_u32(dev, "solomon,dclk-div", &ssd130x->dclk_div)) in ssd130x_parse_properties()
1860 ssd130x->dclk_div = ssd130x->device_info->default_dclk_div; in ssd130x_parse_properties()
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| /drivers/gpu/drm/rockchip/ |
| A D | rockchip_vop2_reg.c | 1455 u32 ctrl, vp_clk_div, reg, dclk_div; in rk3576_set_intf_mux() local
1459 dclk_div = 2; in rk3576_set_intf_mux()
1461 dclk_div = 1; in rk3576_set_intf_mux()
1468 dclk_in_rate = adjusted_mode->crtc_clock / dclk_div; in rk3576_set_intf_mux()
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