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Searched refs:dclk_max (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_5_ppt.c1007 uint32_t dclk_min = 0, dclk_max = 0; in smu_v13_0_5_set_performance_level() local
1014 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max); in smu_v13_0_5_set_performance_level()
1017 dclk_min = dclk_max; in smu_v13_0_5_set_performance_level()
1025 dclk_max = dclk_min; in smu_v13_0_5_set_performance_level()
1030 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max); in smu_v13_0_5_set_performance_level()
1037 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max); in smu_v13_0_5_set_performance_level()
1073 if (dclk_min && dclk_max) { in smu_v13_0_5_set_performance_level()
1077 dclk_max, in smu_v13_0_5_set_performance_level()
A Dsmu_v13_0_4_ppt.c972 uint32_t dclk_min = 0, dclk_max = 0; in smu_v13_0_4_set_performance_level() local
981 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max); in smu_v13_0_4_set_performance_level()
986 dclk_min = dclk_max; in smu_v13_0_4_set_performance_level()
998 dclk_max = dclk_min; in smu_v13_0_4_set_performance_level()
1005 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max); in smu_v13_0_4_set_performance_level()
1015 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max); in smu_v13_0_4_set_performance_level()
1064 if (dclk_min && dclk_max) { in smu_v13_0_4_set_performance_level()
1068 dclk_max); in smu_v13_0_4_set_performance_level()
A Dyellow_carp_ppt.c1204 uint32_t dclk_min = 0, dclk_max = 0; in yellow_carp_set_performance_level() local
1214 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max); in yellow_carp_set_performance_level()
1219 dclk_min = dclk_max; in yellow_carp_set_performance_level()
1231 dclk_max = dclk_min; in yellow_carp_set_performance_level()
1238 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max); in yellow_carp_set_performance_level()
1248 yellow_carp_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max); in yellow_carp_set_performance_level()
1301 if (dclk_min && dclk_max) { in yellow_carp_set_performance_level()
1305 dclk_max, in yellow_carp_set_performance_level()
A Dsmu_v13_0.c1606 uint32_t dclk_min = 0, dclk_max = 0; in smu_v13_0_set_performance_level() local
1617 dclk_min = dclk_max = dclk_table->max; in smu_v13_0_set_performance_level()
1625 dclk_min = dclk_max = dclk_table->min; in smu_v13_0_set_performance_level()
1638 dclk_max = dclk_table->max; in smu_v13_0_set_performance_level()
1648 dclk_min = dclk_max = pstate_table->dclk_pstate.standard; in smu_v13_0_set_performance_level()
1662 dclk_min = dclk_max = pstate_table->dclk_pstate.peak; in smu_v13_0_set_performance_level()
1681 dclk_min = dclk_max = 0; in smu_v13_0_set_performance_level()
1741 if (dclk_min && dclk_max) { in smu_v13_0_set_performance_level()
1748 dclk_max, in smu_v13_0_set_performance_level()
1754 pstate_table->dclk_pstate.curr.max = dclk_max; in smu_v13_0_set_performance_level()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_0_ppt.c1367 uint32_t dclk_min = 0, dclk_max = 0; in smu_v14_0_common_set_performance_level() local
1378 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max); in smu_v14_0_common_set_performance_level()
1385 dclk_min = dclk_max; in smu_v14_0_common_set_performance_level()
1401 dclk_max = dclk_min; in smu_v14_0_common_set_performance_level()
1410 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max); in smu_v14_0_common_set_performance_level()
1422 smu_v14_0_common_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max); in smu_v14_0_common_set_performance_level()
1487 if (dclk_min && dclk_max) { in smu_v14_0_common_set_performance_level()
1491 dclk_max, in smu_v14_0_common_set_performance_level()
A Dsmu_v14_0.c1269 uint32_t dclk_min = 0, dclk_max = 0; in smu_v14_0_set_performance_level() local
1280 dclk_min = dclk_max = dclk_table->max; in smu_v14_0_set_performance_level()
1288 dclk_min = dclk_max = dclk_table->min; in smu_v14_0_set_performance_level()
1301 dclk_max = dclk_table->max; in smu_v14_0_set_performance_level()
1311 dclk_min = dclk_max = pstate_table->dclk_pstate.standard; in smu_v14_0_set_performance_level()
1325 dclk_min = dclk_max = pstate_table->dclk_pstate.peak; in smu_v14_0_set_performance_level()
1391 if (dclk_min && dclk_max) { in smu_v14_0_set_performance_level()
1398 dclk_max, in smu_v14_0_set_performance_level()
1404 pstate_table->dclk_pstate.curr.max = dclk_max; in smu_v14_0_set_performance_level()
/drivers/video/fbdev/riva/
A Drivafb.h49 unsigned dclk_max; /* max DCLK */ member
A Dfbdev.c2005 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; in rivafb_probe()
/drivers/gpu/drm/i915/display/
A Dintel_bw.c471 int dclk_max; in icl_get_bw_info() local
483 dclk_max = icl_sagv_max_dclk(&qi); in icl_get_bw_info()
484 maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10); in icl_get_bw_info()
542 int dclk_max; in tgl_get_bw_info() local
569 dclk_max = icl_sagv_max_dclk(&qi); in tgl_get_bw_info()
571 peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max; in tgl_get_bw_info()

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