| /drivers/gpu/drm/ast/ |
| A D | ast_tables.h | 36 static const struct ast_vbios_dclk_info dclk_table[] = { variable
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| A D | ast_mode.c | 378 clk_info = &dclk_table[vmode->dclk_index]; in ast_set_dclk_reg()
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | arcturus_ppt.h | 65 struct arcturus_single_dpm_table dclk_table; member
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| A D | arcturus_ppt.c | 889 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in arcturus_emit_clk_levels()
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| A D | sienna_cichlid_ppt.c | 1062 dpm_table = &dpm_context->dpm_tables.dclk_table; in sienna_cichlid_set_default_dpm_table()
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| A D | navi10_ppt.c | 1046 dpm_table = &dpm_context->dpm_tables.dclk_table; in navi10_set_default_dpm_table()
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| /drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | aldebaran_ppt.h | 65 struct aldebaran_single_dpm_table dclk_table; member
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| A D | smu_v13_0_7_ppt.c | 673 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_7_set_default_dpm_table()
897 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_7_get_dpm_ultimate_freq()
1217 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_7_print_clk_levels()
2009 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_7_force_clk_levels()
2299 struct smu_13_0_dpm_table *dclk_table = in smu_v13_0_7_populate_umd_state_clk() local
2300 &dpm_context->dpm_tables.dclk_table; in smu_v13_0_7_populate_umd_state_clk()
2326 pstate_table->dclk_pstate.min = dclk_table->min; in smu_v13_0_7_populate_umd_state_clk()
2327 pstate_table->dclk_pstate.peak = dclk_table->max; in smu_v13_0_7_populate_umd_state_clk()
2340 pstate_table->dclk_pstate.standard = dclk_table->min; in smu_v13_0_7_populate_umd_state_clk()
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| A D | smu_v13_0_0_ppt.c | 675 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_0_set_default_dpm_table()
908 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_0_get_dpm_ultimate_freq()
1228 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_0_print_clk_levels()
2020 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_0_force_clk_levels()
2313 struct smu_13_0_dpm_table *dclk_table = in smu_v13_0_0_populate_umd_state_clk() local
2314 &dpm_context->dpm_tables.dclk_table; in smu_v13_0_0_populate_umd_state_clk()
2340 pstate_table->dclk_pstate.min = dclk_table->min; in smu_v13_0_0_populate_umd_state_clk()
2341 pstate_table->dclk_pstate.peak = dclk_table->max; in smu_v13_0_0_populate_umd_state_clk()
2354 pstate_table->dclk_pstate.standard = dclk_table->min; in smu_v13_0_0_populate_umd_state_clk()
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| A D | smu_v13_0.c | 1595 struct smu_13_0_dpm_table *dclk_table = in smu_v13_0_set_performance_level() local
1596 &dpm_context->dpm_tables.dclk_table; in smu_v13_0_set_performance_level()
1617 dclk_min = dclk_max = dclk_table->max; in smu_v13_0_set_performance_level()
1625 dclk_min = dclk_max = dclk_table->min; in smu_v13_0_set_performance_level()
1637 dclk_min = dclk_table->min; in smu_v13_0_set_performance_level()
1638 dclk_max = dclk_table->max; in smu_v13_0_set_performance_level()
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| A D | aldebaran_ppt.c | 373 dpm_table = &dpm_context->dpm_tables.dclk_table; in aldebaran_get_dpm_ultimate_freq()
941 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in aldebaran_emit_clk_levels()
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| A D | smu_v13_0_6_ppt.c | 913 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_6_get_dpm_ultimate_freq()
1010 &dpm_context->dpm_tables.dclk_table, in smu_v13_0_6_set_default_dpm_table()
1495 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_6_print_clk_levels()
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| /drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| A D | smu_v14_0_2_ppt.c | 605 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v14_0_2_set_default_dpm_table()
826 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v14_0_2_get_dpm_ultimate_freq()
1089 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v14_0_2_print_clk_levels()
1415 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v14_0_2_force_clk_levels()
1593 struct smu_14_0_dpm_table *dclk_table = in smu_v14_0_2_populate_umd_state_clk() local
1594 &dpm_context->dpm_tables.dclk_table; in smu_v14_0_2_populate_umd_state_clk()
1620 pstate_table->dclk_pstate.min = dclk_table->min; in smu_v14_0_2_populate_umd_state_clk()
1621 pstate_table->dclk_pstate.peak = dclk_table->max; in smu_v14_0_2_populate_umd_state_clk()
1634 pstate_table->dclk_pstate.standard = dclk_table->min; in smu_v14_0_2_populate_umd_state_clk()
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| A D | smu_v14_0.c | 1258 struct smu_14_0_dpm_table *dclk_table = in smu_v14_0_set_performance_level() local
1259 &dpm_context->dpm_tables.dclk_table; in smu_v14_0_set_performance_level()
1280 dclk_min = dclk_max = dclk_table->max; in smu_v14_0_set_performance_level()
1288 dclk_min = dclk_max = dclk_table->min; in smu_v14_0_set_performance_level()
1300 dclk_min = dclk_table->min; in smu_v14_0_set_performance_level()
1301 dclk_max = dclk_table->max; in smu_v14_0_set_performance_level()
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| /drivers/gpu/drm/amd/pm/swsmu/inc/ |
| A D | smu_v14_0.h | 96 struct smu_14_0_dpm_table dclk_table; member
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| A D | smu_v11_0.h | 108 struct smu_11_0_dpm_table dclk_table; member
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| A D | smu_v13_0.h | 101 struct smu_13_0_dpm_table dclk_table; member
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | vega10_hwmgr.h | 152 struct vega10_single_dpm_table dclk_table; member
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| A D | vega12_hwmgr.h | 130 struct vega12_single_dpm_table dclk_table; member
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| A D | vega20_hwmgr.h | 183 struct vega20_single_dpm_table dclk_table; member
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| A D | vega12_hwmgr.c | 719 dpm_table = &(data->dpm_table.dclk_table); in vega12_setup_default_dpm_tables()
1203 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; in vega12_upload_dpm_min_level()
1288 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; in vega12_upload_dpm_max_level()
2459 dpm_table = &(data->dpm_table.dclk_table); in vega12_apply_clocks_adjust_rules()
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| A D | vega20_hwmgr.c | 706 dpm_table = &(data->dpm_table.dclk_table); in vega20_setup_default_dpm_tables()
1860 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; in vega20_upload_dpm_min_level()
1963 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; in vega20_upload_dpm_max_level()
3857 dpm_table = &(data->dpm_table.dclk_table); in vega20_apply_clocks_adjust_rules()
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| A D | vega10_hwmgr.c | 1396 data->dpm_table.dclk_table.count = 0; in vega10_setup_default_dpm_tables()
1410 dpm_table = &(data->dpm_table.dclk_table); in vega10_setup_default_dpm_tables()
2086 &(data->dpm_table.dclk_table); in vega10_populate_smc_uvd_levels()
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