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Searched refs:dcn (Results 1 – 25 of 45) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c191 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
192 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
193 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
194 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
195 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
196 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
199 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
200 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
201 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
203 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c295 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
318 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
329 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = in dcn30_fpu_calculate_wm_and_dlg()
332 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
370 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
423 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
453 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; in dcn30_fpu_calculate_wm_and_dlg()
454 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; in dcn30_fpu_calculate_wm_and_dlg()
476 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn30_fpu_calculate_wm_and_dlg()
498 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && in dcn30_fpu_calculate_wm_and_dlg()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_wrapper.c98 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml21_calculate_rq_and_dlg_params()
106 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
107 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
108 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
142 memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], in dml21_calculate_rq_and_dlg_params()
151 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml21_calculate_rq_and_dlg_params()
152 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml21_calculate_rq_and_dlg_params()
154 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in dml21_calculate_rq_and_dlg_params()
161 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dml21_calculate_rq_and_dlg_params()
169 …context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, cont… in dml21_calculate_rq_and_dlg_params()
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A Ddml21_utils.c177 context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
181 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
231 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz) in dml21_program_dc_pipe()
232 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz; in dml21_program_dc_pipe()
385 …memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * … in dml21_build_fams2_programming()
386 …memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * D… in dml21_build_fams2_programming()
388 …memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)… in dml21_build_fams2_programming()
420 memcpy(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2[num_fams2_streams], in dml21_build_fams2_programming()
503 memcpy(&context->bw_ctx.bw.dcn.fams2_global_config, in dml21_build_fams2_programming()
507 context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams; in dml21_build_fams2_programming()
[all …]
A Ddml21_translation_helper.c1154 …context->bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1155 …context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x… in dml21_copy_clocks_to_dc_state()
1156 …context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1157 …context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.a… in dml21_copy_clocks_to_dc_state()
1158 …context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks… in dml21_copy_clocks_to_dc_state()
1159 …context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dc… in dml21_copy_clocks_to_dc_state()
1161 …context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming-… in dml21_copy_clocks_to_dc_state()
1162 …context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk… in dml21_copy_clocks_to_dc_state()
1163 …context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.… in dml21_copy_clocks_to_dc_state()
1164 …context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.d… in dml21_copy_clocks_to_dc_state()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_utils.c184 context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz; in dml2_copy_clocks_to_dc_state()
185 context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz; in dml2_copy_clocks_to_dc_state()
187 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; in dml2_copy_clocks_to_dc_state()
188 context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz; in dml2_copy_clocks_to_dc_state()
189 context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz; in dml2_copy_clocks_to_dc_state()
286 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml2_calculate_rq_and_dlg_params()
361 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml2_calculate_rq_and_dlg_params()
362 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml2_calculate_rq_and_dlg_params()
370 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dml2_calculate_rq_and_dlg_params()
371 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz ; in dml2_calculate_rq_and_dlg_params()
[all …]
A Ddml2_wrapper.c419 context->bw_ctx.bw.dcn.clk.dtbclk_en = false; in dml2_validate_and_build_resource()
477 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(in_dc, context); in dml2_validate_and_build_resource()
485 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
486 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
488 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
490 …memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context… in dml2_validate_and_build_resource()
491 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
496 …cstate_enter_plus_exit_z8_ns = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus… in dml2_validate_and_build_resource()
502 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus… in dml2_validate_and_build_resource()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c533 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
534 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
535 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
561 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn31_calculate_wm_and_dlg_fp()
565 context->bw_ctx.bw.dcn.clk.socclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
566 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
567 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
568 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
569 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
570 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c630 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
631 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
634 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1153 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1154 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1155 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1169 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth()
1171 context->bw_ctx.bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth()
1175 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / in dcn_validate_bandwidth()
1180 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1160 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; in dcn20_calculate_dlg_params()
1164 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn20_calculate_dlg_params()
1171 …context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_swit… in dcn20_calculate_dlg_params()
1173 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dcn20_calculate_dlg_params()
1175 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); in dcn20_calculate_dlg_params()
1178 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; in dcn20_calculate_dlg_params()
1214 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; in dcn20_calculate_dlg_params()
1217 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dcn20_calculate_dlg_params()
1218 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dcn20_calculate_dlg_params()
1242 context->bw_ctx.bw.dcn.clk.p_state_change_support, in dcn20_calculate_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c1672 …context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_swit… in dcn32_calculate_dlg_params()
1674 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dcn32_calculate_dlg_params()
1768 context->bw_ctx.bw.dcn.clk.socclk_khz = 0; in dcn32_calculate_dlg_params()
1769 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dcn32_calculate_dlg_params()
1770 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; in dcn32_calculate_dlg_params()
1772 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; in dcn32_calculate_dlg_params()
1773 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; in dcn32_calculate_dlg_params()
1778 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dcn32_calculate_dlg_params()
1779 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dcn32_calculate_dlg_params()
2561 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; in dcn32_calculate_wm_and_dlg_fpu()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hw_sequencer_debug.c478 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_get_clock_states()
479 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
480 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
481 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
482 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
483 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_get_clock_states()
/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c434 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_fpu_calculate_wm_and_dlg()
439 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn301_fpu_calculate_wm_and_dlg()
444 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn301_fpu_calculate_wm_and_dlg()
450 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn301_fpu_calculate_wm_and_dlg()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c94 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
533 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down) in dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch()
778 …if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_K… in dcn32_override_min_req_dcfclk()
779 context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ; in dcn32_override_min_req_dcfclk()
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c56 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
1232 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn401_calculate_cab_allocation()
1360 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn401_prepare_bandwidth()
1366 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn401_prepare_bandwidth()
1385 &context->bw_ctx.bw.dcn.watermarks, in dcn401_prepare_bandwidth()
1395 compbuf_size = context->bw_ctx.bw.dcn.arb_regs.compbuf_size; in dcn401_prepare_bandwidth()
1410 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; in dcn401_prepare_bandwidth()
1430 &context->bw_ctx.bw.dcn.watermarks, in dcn401_optimize_bandwidth()
1435 hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, true); in dcn401_optimize_bandwidth()
1451 if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { in dcn401_optimize_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/
A Ddc_dmub_srv.c935 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * in dc_dmub_setup_subvp_dmub_command()
1717 for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) { in dc_dmub_srv_rb_based_fams2_update_config()
1734 &context->bw_ctx.bw.dcn.fams2_stream_base_params[i], in dc_dmub_srv_rb_based_fams2_update_config()
1738 &context->bw_ctx.bw.dcn.fams2_stream_sub_params[i], in dc_dmub_srv_rb_based_fams2_update_config()
1747 if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) { in dc_dmub_srv_rb_based_fams2_update_config()
1751 num_cmds += 2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams; in dc_dmub_srv_rb_based_fams2_update_config()
1774 if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) { in dc_dmub_srv_ib_based_fams2_update_config()
1781 memcpy(&config->global, &context->bw_ctx.bw.dcn.fams2_global_config, in dc_dmub_srv_ib_based_fams2_update_config()
1785 for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) { in dc_dmub_srv_ib_based_fams2_update_config()
1788 &context->bw_ctx.bw.dcn.fams2_stream_base_params[i], in dc_dmub_srv_ib_based_fams2_update_config()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c226 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn32_calculate_cab_allocation()
749 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn32_initialize_min_clocks()
1789 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn32_prepare_bandwidth()
1793 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
1795 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn32_prepare_bandwidth()
1800 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn32_prepare_bandwidth()
1805 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn32_prepare_bandwidth()
1808 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
1812 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; in dcn32_prepare_bandwidth()
1846 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); in dcn32_program_outstanding_updates()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c432 mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn401_auto_dpm_test_log()
1229 &context->bw_ctx.bw.dcn.clk, in dcn401_update_clocks()
1238 &context->bw_ctx.bw.dcn.clk, in dcn401_update_clocks()
1245 dcn401_auto_dpm_test_log(&context->bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context); in dcn401_update_clocks()
1342 new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz; in dcn401_set_hard_min_memclk()
1343 new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz; in dcn401_set_hard_min_memclk()
1344 new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn401_set_hard_min_memclk()
1364 return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.dramclk_khz; in dcn401_get_hard_min_memclk()
1371 return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz; in dcn401_get_hard_min_fclk()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c2374 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; in dcn20_prepare_bandwidth()
2387 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_prepare_bandwidth()
2397 &context->bw_ctx.bw.dcn.watermarks, in dcn20_prepare_bandwidth()
2403 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; in dcn20_prepare_bandwidth()
2411 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; in dcn20_prepare_bandwidth()
2431 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_optimize_bandwidth()
2438 &context->bw_ctx.bw.dcn.watermarks, in dcn20_optimize_bandwidth()
2449 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); in dcn20_optimize_bandwidth()
2451 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn20_optimize_bandwidth()
2454 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; in dcn20_optimize_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c706 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_log_hw_state()
708 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
709 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_log_hw_state()
711 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_log_hw_state()
712 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_log_hw_state()
2986 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn10_update_dchubp_dpp()
2991 context->bw_ctx.bw.dcn.clk.dppclk_khz <= in dcn10_update_dchubp_dpp()
3308 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_prepare_bandwidth()
3316 &context->bw_ctx.bw.dcn.watermarks, in dcn10_prepare_bandwidth()
3346 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_optimize_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c446 …mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info-… in dcn30_set_writeback()
1168 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) && in dcn30_hardware_release()
1189 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switchi… in dcn30_prepare_bandwidth()
1191 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn30_prepare_bandwidth()
1196 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn30_prepare_bandwidth()
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_helpers.c1324 dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dm_helpers_dp_handle_test_pattern_request()
1325 dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ? in dm_helpers_dp_handle_test_pattern_request()
1327 dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz; in dm_helpers_dp_handle_test_pattern_request()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
A Ddcn201_clk_mgr.c89 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c141 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn316_update_clocks()
238 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) in dcn316_update_clocks()

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