Searched refs:dcn4x (Results 1 – 13 of 13) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/hubbub/dcn401/ |
| A D | dcn401_hubbub.c | 79 hubbub2->watermarks.dcn4x.a.urgent = watermarks->dcn4x.a.urgent; in hubbub401_program_urgent_watermarks()
84 watermarks->dcn4x.a.urgent, watermarks->dcn4x.a.urgent); in hubbub401_program_urgent_watermarks()
137 watermarks->dcn4x.b.urgent, watermarks->dcn4x.b.urgent); in hubbub401_program_urgent_watermarks()
203 watermarks->dcn4x.a.sr_enter, watermarks->dcn4x.a.sr_enter); in hubbub401_program_stutter_watermarks()
224 watermarks->dcn4x.a.sr_exit, watermarks->dcn4x.a.sr_exit); in hubbub401_program_stutter_watermarks()
246 watermarks->dcn4x.b.sr_enter, watermarks->dcn4x.b.sr_enter); in hubbub401_program_stutter_watermarks()
267 watermarks->dcn4x.b.sr_exit, watermarks->dcn4x.b.sr_exit); in hubbub401_program_stutter_watermarks()
423 hubbub2->watermarks.dcn4x.a.usr = watermarks->dcn4x.a.usr; in hubbub401_program_usr_watermarks()
428 watermarks->dcn4x.a.usr, watermarks->dcn4x.a.usr); in hubbub401_program_usr_watermarks()
436 hubbub2->watermarks.dcn4x.b.usr = watermarks->dcn4x.b.usr; in hubbub401_program_usr_watermarks()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/ |
| A D | dml2_dpmm_dcn4.c | 355 display_cfg->min_clocks.dcn4x.svp_prefetch.dcfclk_khz = 0; in map_soc_min_clocks_to_dpm_coarse_grained()
356 display_cfg->min_clocks.dcn4x.svp_prefetch.fclk_khz = 0; in map_soc_min_clocks_to_dpm_coarse_grained()
357 display_cfg->min_clocks.dcn4x.svp_prefetch.uclk_khz = 0; in map_soc_min_clocks_to_dpm_coarse_grained()
602 …if (in_out->programming->min_clocks.dcn4x.svp_prefetch.uclk_khz > in_out->programming->min_clocks.… in map_mode_to_soc_dpm()
603 …in_out->programming->min_clocks.dcn4x.active.uclk_khz = in_out->programming->min_clocks.dcn4x.svp_… in map_mode_to_soc_dpm()
605 …if (in_out->programming->min_clocks.dcn4x.svp_prefetch.fclk_khz > in_out->programming->min_clocks.… in map_mode_to_soc_dpm()
606 …in_out->programming->min_clocks.dcn4x.active.fclk_khz = in_out->programming->min_clocks.dcn4x.svp_… in map_mode_to_soc_dpm()
608 …if (in_out->programming->min_clocks.dcn4x.svp_prefetch.dcfclk_khz > in_out->programming->min_clock… in map_mode_to_soc_dpm()
609 …in_out->programming->min_clocks.dcn4x.active.dcfclk_khz = in_out->programming->min_clocks.dcn4x.sv… in map_mode_to_soc_dpm()
634 …gramming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_… in map_mode_to_soc_dpm()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 1154 …tx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dispclk_khz; in dml21_copy_clocks_to_dc_state()
1155 …context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x… in dml21_copy_clocks_to_dc_state()
1156 …w.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.uclk_khz; in dml21_copy_clocks_to_dc_state()
1157 …context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.a… in dml21_copy_clocks_to_dc_state()
1159 …w.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.idle.fclk_khz; in dml21_copy_clocks_to_dc_state()
1163 …context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.… in dml21_copy_clocks_to_dc_state()
1165 …context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x… in dml21_copy_clocks_to_dc_state()
1176 wm_regs = &watermarks->dcn4x.a; in wm_set_index_to_dc_wm_set()
1179 wm_regs = &watermarks->dcn4x.b; in wm_set_index_to_dc_wm_set()
1182 wm_regs = &watermarks->dcn4x.c; in wm_set_index_to_dc_wm_set()
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| A D | dml21_utils.c | 230 pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4x.dppclk_khz; in dml21_program_dc_pipe()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_types.h | 221 } dcn4x; member
257 } dcn4x; member
268 } dcn4x; member
408 } dcn4x; member
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| A D | dml_top_soc_parameter_types.h | 84 struct dml2_dcn4x_soc_qos_params dcn4x; member
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 820 (unsigned int)pipe_ctx->global_sync.dcn4x.vready_offset_pixels, in dcn401_enable_stream_timing()
821 (unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines, in dcn401_enable_stream_timing()
822 (unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels, in dcn401_enable_stream_timing()
824 (unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines, in dcn401_enable_stream_timing()
1915 vready_offset = other_pipe->global_sync.dcn4x.vready_offset_pixels; in dcn401_calculate_vready_offset_for_group()
1919 vready_offset = other_pipe->global_sync.dcn4x.vready_offset_pixels; in dcn401_calculate_vready_offset_for_group()
1923 vready_offset = other_pipe->global_sync.dcn4x.vready_offset_pixels; in dcn401_calculate_vready_offset_for_group()
1942 (unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines, in dcn401_program_tg()
1943 (unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels, in dcn401_program_tg()
2403 (unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines, in dcn401_update_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/ |
| A D | dcn4_soc_bb.h | 55 .dcn4x = {
181 .dcn4x = {
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | mem_input.h | 66 } dcn4x; //dcn4+ member
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| A D | dcn401_hubp.c | 151 unsigned int vstartup_lines = pipe_global_sync->dcn4x.vstartup_lines; in hubp401_vready_at_or_After_vsync()
152 unsigned int vupdate_offset_pixels = pipe_global_sync->dcn4x.vupdate_offset_pixels; in hubp401_vready_at_or_After_vsync()
153 unsigned int vupdate_width_pixels = pipe_global_sync->dcn4x.vupdate_vupdate_width_pixels; in hubp401_vready_at_or_After_vsync()
154 unsigned int vready_offset_pixels = pipe_global_sync->dcn4x.vready_offset_pixels; in hubp401_vready_at_or_After_vsync()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_dcn4_calcs.c | 7240 struct dml2_dcn4x_soc_qos_params *dcn4x, in get_max_urgent_latency_us() argument
7247 * (1 + dcn4x->umc_max_latency_margin / 100.0) in get_max_urgent_latency_us()
7248 + dcn4x->mall_overhead_fclk_cycles / FabricClock in get_max_urgent_latency_us()
7249 + dcn4x->max_round_trip_to_furthest_cs_fclk_cycles / FabricClock in get_max_urgent_latency_us()
7250 * (1 + dcn4x->fabric_max_transport_latency_margin / 100.0); in get_max_urgent_latency_us()
9052 mode_lib->soc.qos_parameters.qos_params.dcn4x.mall_overhead_fclk_cycles, in dml_core_mode_support()
9064 mode_lib->soc.qos_parameters.qos_params.dcn4x.umc_max_latency_margin, in dml_core_mode_support()
10379 s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; in dml_core_mode_programming()
10380 …t_qos_param_index(programming->min_clocks.dcn4x.active.uclk_khz, mode_lib->soc.qos_parameters.qos_… in dml_core_mode_programming()
11022 mode_lib->soc.qos_parameters.qos_params.dcn4x.umc_max_latency_margin, in dml_core_mode_programming()
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| A D | dml2_core_dcn4.c | 561 …in_clk_index = lookup_uclk_dpm_index_by_freq(in_out->programming->min_clocks.dcn4x.active.uclk_khz, in core_dcn4_mode_programming()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 1770 return pipe_ctx->global_sync.dcn4x.vstartup_lines; in dcn401_get_vstartup_for_pipe()
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