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Searched refs:dcn_pipe_count (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_mall_phantom.c49 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in dml2_helper_calculate_num_ways_for_subvp()
106 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in merge_pipes_for_subvp()
150 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in all_pipes_have_stream_and_plane()
191 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in get_num_free_pipes()
202 free_pipes = ctx->config.dcn_pipe_count - num_pipes; in get_num_free_pipes()
315 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in enough_pipes_for_subvp()
367 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in subvp_subvp_schedulable()
448 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in dml2_svp_drr_schedulable()
533 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in subvp_vblank_schedulable()
795 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in add_phantom_pipes_for_main_pipe()
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A Ddml2_dc_resource_mgmt.c113 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in find_master_pipe_of_stream()
129 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in find_master_pipe_of_plane()
148 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in find_pipes_assigned_to_plane()
357 …find_preferred_pipe_candidates(existing_state, ctx->config.dcn_pipe_count, stream_id, preferred_pi… in find_more_pipes_for_stream()
360 …find_last_resort_pipe_candidates(existing_state, ctx->config.dcn_pipe_count, stream_id, last_resor… in find_more_pipes_for_stream()
375 for (i = ctx->config.dcn_pipe_count - 1; pipes_needed > 0 && i >= 0; i--) { in find_more_pipes_for_stream()
423 …find_preferred_pipe_candidates(existing_state, ctx->config.dcn_pipe_count, stream_id, preferred_pi… in find_more_free_pipes()
441 for (i = ctx->config.dcn_pipe_count - 1; pipes_needed > 0 && i >= 0; i--) { in find_more_free_pipes()
590 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in find_pipes_assigned_to_stream()
708 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in free_unused_pipes_for_plane()
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A Ddml2_wrapper.h210 int dcn_pipe_count; member
A Ddml2_wrapper.c173 for (i = 0; i < dml2->config.dcn_pipe_count; i++) { in calculate_lowest_supported_state_for_temp_read()
281 for (i = 0; i < dml2->config.dcn_pipe_count; i++) { in dml_mode_support_wrapper()
A Ddml2_translation_helper.c63 out->max_num_dpp = dml2->config.dcn_pipe_count; in dml2_init_ip_params()
64 out->max_num_otg = dml2->config.dcn_pipe_count; in dml2_init_ip_params()
198 out->max_num_dpp = dml2->config.dcn_pipe_count; in dml2_init_ip_params()
199 out->max_num_otg = dml2->config.dcn_pipe_count; in dml2_init_ip_params()
A Ddml2_utils.c494 dml_dispcfg->plane.DETSizeOverride[plane_index] = max_det_size / in_ctx->config.dcn_pipe_count; in dml2_apply_det_buffer_allocation_policy()
/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c2017 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn321_resource_construct()
/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.c2166 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn35_resource_construct()
/drivers/gpu/drm/amd/display/dc/resource/dcn351/
A Ddcn351_resource.c2138 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn351_resource_construct()
/drivers/gpu/drm/amd/display/dc/resource/dcn36/
A Ddcn36_resource.c2139 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn36_resource_construct()
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c2212 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn401_resource_construct()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c2518 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn32_resource_construct()

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