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Searched refs:dct (Results 1 – 11 of 11) sorted by relevance

/drivers/infiniband/hw/mlx5/
A Dqpc.c13 struct mlx5_core_dct *dct);
95 struct mlx5_core_dct *dct; in dct_event_notifier() local
102 if (dct) in dct_event_notifier()
103 complete(&dct->drained); in dct_event_notifier()
210 struct mlx5_core_dct *dct) in _mlx5_core_destroy_dct() argument
227 init_completion(&dct->drained); in mlx5_core_create_dct()
242 _mlx5_core_destroy_dct(dev, dct); in mlx5_core_create_dct()
292 struct mlx5_core_dct *dct) in mlx5_core_destroy_dct() argument
308 tmp = xa_cmpxchg_irq(&table->dct_xa, dct->mqp.qpn, dct, XA_ZERO_ENTRY, GFP_KERNEL); in mlx5_core_destroy_dct()
309 if (WARN_ON(tmp != dct)) in mlx5_core_destroy_dct()
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A Dqp.h31 int mlx5_core_destroy_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct);
34 int mlx5_core_dct_query(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
A Dqp.c2743 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); in create_dct()
2744 if (!qp->dct.in) in create_dct()
2747 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); in create_dct()
3209 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); in mlx5_ib_destroy_dct()
3216 kfree(mqp->dct.in); in mlx5_ib_destroy_dct()
4615 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, in mlx5_ib_modify_dct()
4618 err = mlx5_cmd_check(dev->mdev, err, qp->dct.in, out); in mlx5_ib_modify_dct()
4621 resp.dctn = qp->dct.mdct.mqp.qpn; in mlx5_ib_modify_dct()
4626 mlx5_core_destroy_dct(dev, &qp->dct.mdct); in mlx5_ib_modify_dct()
5036 struct mlx5_core_dct *dct = &mqp->dct.mdct; in mlx5_ib_dct_query_qp() local
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A Ddevx.c695 qp->dct.mdct.mqp.qpn) == obj_id; in devx_is_valid_obj_id()
2483 obj_id = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; in devx_get_obj_id_from_event()
A Dmlx5_ib.h505 struct mlx5_ib_dct dct; member
/drivers/edac/
A Damd64_edac.c110 reg |= dct; in f15h_select_dct()
133 if (dct || offset >= 0x100) in amd64_read_dct_pci_cfg()
138 if (dct) { in amd64_read_dct_pci_cfg()
156 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
157 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
161 if (dct) in amd64_read_dct_pci_cfg()
434 pvt->csels[dct].csbases[i]
3060 csrow_nr, dct, cs_mode); in dct_get_csrow_nr_pages()
3077 csrow_nr_orig, dct, cs_mode); in umc_get_csrow_nr_pages()
3996 int cs = 0, dct = 0; in instance_has_memory() local
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A Damd64_edac.h166 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) argument
167 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE) argument
463 int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
/drivers/soc/fsl/dpio/
A Dqbman-portal.h215 enum qbman_pull_type_e dct);
217 enum qbman_pull_type_e dct);
A Dqbman-portal.c1068 enum qbman_pull_type_e dct) in qbman_pull_desc_set_wq() argument
1070 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; in qbman_pull_desc_set_wq()
1083 enum qbman_pull_type_e dct) in qbman_pull_desc_set_channel() argument
1085 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; in qbman_pull_desc_set_channel()
/drivers/net/ethernet/mellanox/mlx5/core/
A Dmain.c632 if (MLX5_CAP_GEN_MAX(dev, dct)) in handle_hca_cap()
633 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); in handle_hca_cap()
A Deq.c562 if (MLX5_CAP_GEN_MAX(dev, dct)) in gather_async_events_mask()

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