Searched refs:deferred_reg_writes (Results 1 – 5 of 5) sorted by relevance
525 if (dpp_base->deferred_reg_writes.bits.disable_dscl) { in dpp3_deferred_update()527 dpp_base->deferred_reg_writes.bits.disable_dscl = false; in dpp3_deferred_update()530 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) { in dpp3_deferred_update()536 dpp_base->deferred_reg_writes.bits.disable_gamcor = false; in dpp3_deferred_update()539 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) { in dpp3_deferred_update()548 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) { in dpp3_deferred_update()554 dpp_base->deferred_reg_writes.bits.disable_3dlut = false; in dpp3_deferred_update()557 if (dpp_base->deferred_reg_writes.bits.disable_shaper) { in dpp3_deferred_update()563 dpp_base->deferred_reg_writes.bits.disable_shaper = false; in dpp3_deferred_update()599 dpp_base->deferred_reg_writes.bits.disable_3dlut = true; in dpp3_power_on_hdr3dlut()[all …]
138 dpp_base->deferred_reg_writes.bits.disable_gamcor = true; in dpp3_power_on_gamcor_lut()
83 union defer_reg_writes deferred_reg_writes; member
170 dpp->base.deferred_reg_writes.bits.disable_dscl = true; in dpp1_power_on_dscl()
172 dpp->base.deferred_reg_writes.bits.disable_dscl = true; in dpp401_power_on_dscl()
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