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Searched refs:dev_priv (Results 1 – 25 of 163) sorted by relevance

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/drivers/gpu/drm/xe/compat-i915-headers/
A Di915_drv.h26 #define IS_I915G(dev_priv) (dev_priv && 0) argument
27 #define IS_I915GM(dev_priv) (dev_priv && 0) argument
28 #define IS_PINEVIEW(dev_priv) (dev_priv && 0) argument
29 #define IS_IVYBRIDGE(dev_priv) (dev_priv && 0) argument
30 #define IS_VALLEYVIEW(dev_priv) (dev_priv && 0) argument
32 #define IS_HASWELL(dev_priv) (dev_priv && 0) argument
33 #define IS_BROADWELL(dev_priv) (dev_priv && 0) argument
34 #define IS_SKYLAKE(dev_priv) (dev_priv && 0) argument
35 #define IS_BROXTON(dev_priv) (dev_priv && 0) argument
36 #define IS_KABYLAKE(dev_priv) (dev_priv && 0) argument
[all …]
/drivers/gpu/drm/vmwgfx/
A Dvmwgfx_drv.c423 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
425 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_device_init()
434 dev_priv->fifo = vmw_fifo_create(dev_priv); in vmw_device_init()
517 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); in vmw_request_device()
875 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); in vmw_driver_load()
917 dev_priv->memory_size -= dev_priv->vram_size; in vmw_driver_load()
950 dev_priv->texture_max_width = vmw_read(dev_priv, in vmw_driver_load()
954 dev_priv->texture_max_height = vmw_read(dev_priv, in vmw_driver_load()
959 dev_priv->max_primary_mem = dev_priv->vram_size; in vmw_driver_load()
969 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); in vmw_driver_load()
[all …]
A Dvmwgfx_irq.c139 if (!vmw_has_fences(dev_priv) && vmw_fifo_idle(dev_priv, seqno)) in vmw_seqno_passed()
178 if (dev_priv->cman) { in vmw_fallback_wait()
242 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
257 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
278 return vmw_generic_waiter_add(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_add()
284 return vmw_generic_waiter_remove(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_remove()
340 drm_err(&dev_priv->drm, in vmw_irq_install()
351 drm_err(&dev_priv->drm, in vmw_irq_install()
355 dev_priv->irqs[i] = ret; in vmw_irq_install()
360 drm_err(&dev_priv->drm, in vmw_irq_install()
[all …]
A Dvmwgfx_cmd.c47 if (!dev_priv->has_mob) in vmw_supports_3d()
103 if (!dev_priv->fifo_mem) in vmw_fifo_create()
131 vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size); in vmw_fifo_create()
144 drm_info(&dev_priv->drm, in vmw_fifo_create()
151 drm_warn(&dev_priv->drm, in vmw_fifo_create()
184 dev_priv->fifo = NULL; in vmw_fifo_destroy()
370 if (dev_priv->cman) in vmw_cmd_ctx_reserve()
474 if (dev_priv->cman) in vmw_cmd_commit()
489 if (dev_priv->cman) in vmw_cmd_commit_flush()
506 if (dev_priv->cman) in vmw_cmd_flush()
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A Dvmwgfx_context.c144 struct vmw_private *dev_priv = res->dev_priv; in vmw_hw_context_destroy() local
198 if (dev_priv->has_mob) { in vmw_gb_context_init()
253 if (dev_priv->has_mob) in vmw_context_init()
300 struct vmw_private *dev_priv = res->dev_priv; in vmw_gb_context_create() local
344 struct vmw_private *dev_priv = res->dev_priv; in vmw_gb_context_bind() local
372 struct vmw_private *dev_priv = res->dev_priv; in vmw_gb_context_unbind() local
436 struct vmw_private *dev_priv = res->dev_priv; in vmw_gb_context_destroy() local
467 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_context_create() local
511 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_context_bind() local
581 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_context_unbind() local
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A Dvmwgfx_overlay.c119 cmds = VMW_CMD_RESERVE(dev_priv, fifo_size); in vmw_overlay_send_put()
166 vmw_cmd_commit(dev_priv, fifo_size); in vmw_overlay_send_put()
208 vmw_cmd_commit(dev_priv, sizeof(*cmds)); in vmw_overlay_send_stop()
224 return vmw_bo_unpin(dev_priv, buf, inter); in vmw_overlay_move_buffer()
417 return (dev_priv->overlay_priv != NULL && in vmw_overlay_available()
434 if (!vmw_overlay_available(dev_priv)) in vmw_overlay_ioctl()
465 if (!vmw_overlay_available(dev_priv)) in vmw_overlay_num_overlays()
476 if (!vmw_overlay_available(dev_priv)) in vmw_overlay_num_free_overlays()
539 if (dev_priv->overlay_priv) in vmw_overlay_init()
553 dev_priv->overlay_priv = overlay; in vmw_overlay_init()
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A Dvmwgfx_drv.h133 struct vmw_private *dev_priv; member
324 struct vmw_private *dev_priv; member
648 if (vmw_is_svga_v3(dev_priv)) { in vmw_write()
651 spin_lock(&dev_priv->hw_lock); in vmw_write()
654 spin_unlock(&dev_priv->hw_lock); in vmw_write()
663 if (vmw_is_svga_v3(dev_priv)) { in vmw_read()
666 spin_lock(&dev_priv->hw_lock); in vmw_read()
669 spin_unlock(&dev_priv->hw_lock); in vmw_read()
776 struct vmw_private *dev_priv,
888 if (!dev_priv->fifo_mem || !dev_priv->fifo) in vmw_fifo_caps()
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A Dvmwgfx_ldu.c160 vmw_overlay_pause_all(dev_priv); in vmw_ldu_fb_pin()
319 struct vmw_private *dev_priv; in vmw_ldu_primary_plane_atomic_update() local
326 dev_priv = vmw_priv(plane->dev); in vmw_ldu_primary_plane_atomic_update()
336 vmw_ldu_commit_list(dev_priv); in vmw_ldu_primary_plane_atomic_update()
550 dev_priv->ldu_priv = kmalloc(sizeof(*dev_priv->ldu_priv), GFP_KERNEL); in vmw_kms_ldu_init_display()
551 if (!dev_priv->ldu_priv) in vmw_kms_ldu_init_display()
557 dev_priv->ldu_priv->fb = NULL; in vmw_kms_ldu_init_display()
574 kfree(dev_priv->ldu_priv); in vmw_kms_ldu_init_display()
575 dev_priv->ldu_priv = NULL; in vmw_kms_ldu_init_display()
581 if (!dev_priv->ldu_priv) in vmw_kms_ldu_close_display()
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A Dvmwgfx_execbuf.c297 struct vmw_private *dev_priv = res->dev_priv; in vmw_execbuf_res_val_add() local
692 struct vmw_private *dev_priv = ctx_res->dev_priv; in vmw_rebind_all_dx_query() local
875 if (dev_priv->has_mob) { in vmw_cmd_set_render_target_check()
1106 dev_priv->pinned_bo = in vmw_query_bo_switch_commit()
1393 if (dev_priv->has_mob) { in vmw_cmd_end_query()
1467 if (dev_priv->has_mob) { in vmw_cmd_wait_query()
1992 if (!dev_priv->has_mob) in vmw_cmd_set_shader()
2064 if (dev_priv->has_mob) in vmw_cmd_set_shader_const()
4218 if (unlikely(dev_priv->pinned_bo != NULL && !dev_priv->query_cid_valid)) in vmw_execbuf_process()
4281 if (unlikely(dev_priv->pinned_bo != NULL && !dev_priv->query_cid_valid)) in vmw_execbuf_process()
[all …]
A Dvmwgfx_resource.c104 struct vmw_private *dev_priv = res->dev_priv; in vmw_resource_release_id() local
118 struct vmw_private *dev_priv = res->dev_priv; in vmw_resource_release() local
187 struct vmw_private *dev_priv = res->dev_priv; in vmw_resource_alloc_id() local
223 res->dev_priv = dev_priv; in vmw_resource_init()
459 struct vmw_private *dev_priv = res->dev_priv; in vmw_resource_unreserve() local
582 struct vmw_private *dev_priv = res->dev_priv; in vmw_resource_reserve() local
686 struct vmw_private *dev_priv = res->dev_priv; in vmw_resource_validate() local
796 struct vmw_private *dev_priv; in vmw_query_readback_all() local
808 dev_priv = dx_query_ctx->dev_priv; in vmw_query_readback_all()
969 struct vmw_private *dev_priv = res->dev_priv; in vmw_resource_pin() local
[all …]
A Dvmwgfx_ioctl.c55 param->value = dev_priv->capabilities; in vmw_getparam_ioctl()
58 param->value = dev_priv->capabilities2; in vmw_getparam_ioctl()
61 param->value = vmw_fifo_caps(dev_priv); in vmw_getparam_ioctl()
64 param->value = dev_priv->max_primary_mem; in vmw_getparam_ioctl()
72 dev_priv, in vmw_getparam_ioctl()
73 ((vmw_fifo_caps(dev_priv) & in vmw_getparam_ioctl()
84 param->value = dev_priv->memory_size; in vmw_getparam_ioctl()
94 param->value = dev_priv->max_mob_size; in vmw_getparam_ioctl()
101 param->value = has_sm4_context(dev_priv); in vmw_getparam_ioctl()
107 param->value = has_sm5_context(dev_priv); in vmw_getparam_ioctl()
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/drivers/gpu/drm/i915/
A Di915_irq.c173 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) in ivb_parity_work()
210 drm_dbg(&dev_priv->drm, in ivb_parity_work()
223 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); in ivb_parity_work()
668 dev_priv->irq_mask = ~0u; in ilk_irq_reset()
905 dev_priv->irq_mask = ~0u; in i915_irq_reset()
916 dev_priv->irq_mask = in i915_irq_postinstall()
1037 dev_priv->irq_mask = in i965_irq_postinstall()
1052 if (IS_G4X(dev_priv)) in i965_irq_postinstall()
1136 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11) in intel_irq_init()
1263 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->irqs_enabled)) in intel_irq_uninstall()
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A Di915_driver.c179 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; in intel_detect_preproduction_hw()
180 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; in intel_detect_preproduction_hw()
181 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
182 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; in intel_detect_preproduction_hw()
183 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; in intel_detect_preproduction_hw()
184 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
185 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
186 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; in intel_detect_preproduction_hw()
187 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; in intel_detect_preproduction_hw()
188 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
[all …]
A Dintel_gvt.c54 if (IS_BROADWELL(dev_priv)) in is_supported_device()
56 if (IS_SKYLAKE(dev_priv)) in is_supported_device()
58 if (IS_KABYLAKE(dev_priv)) in is_supported_device()
60 if (IS_BROXTON(dev_priv)) in is_supported_device()
64 if (IS_COMETLAKE(dev_priv)) in is_supported_device()
129 iter.i915 = dev_priv; in save_initial_hw_state()
152 drm_dbg(&dev_priv->drm, in intel_gvt_init_device()
163 drm_info(&dev_priv->drm, in intel_gvt_init_device()
169 drm_err(&dev_priv->drm, in intel_gvt_init_device()
185 if (dev_priv->gvt) in intel_gvt_clean_device()
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A Di915_vgpu.c77 if (GRAPHICS_VER(dev_priv) < 6) in intel_vgpu_detect()
82 drm_err(&dev_priv->drm, in intel_vgpu_detect()
99 dev_priv->vgpu.active = true; in intel_vgpu_detect()
100 mutex_init(&dev_priv->vgpu.lock); in intel_vgpu_detect()
119 return dev_priv->vgpu.active; in intel_vgpu_active()
134 return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT; in intel_vgpu_has_huge_gtt()
155 drm_dbg(&dev_priv->drm, in vgt_deballoon_space()
180 drm_dbg(&dev_priv->drm, "VGT deballoon.\n"); in intel_vgt_deballoon()
197 drm_info(&dev_priv->drm, in vgt_balloon_space()
279 drm_info(&dev_priv->drm, in intel_vgt_balloon()
[all …]
A Dintel_gvt_mmio_table.c136 MMIO_D(PIPEDSL(dev_priv, PIPE_A)); in iterate_generic_mmio()
159 MMIO_D(CURPOS(dev_priv, PIPE_A)); in iterate_generic_mmio()
160 MMIO_D(CURPOS(dev_priv, PIPE_B)); in iterate_generic_mmio()
161 MMIO_D(CURPOS(dev_priv, PIPE_C)); in iterate_generic_mmio()
178 MMIO_D(DSPPOS(dev_priv, PIPE_A)); in iterate_generic_mmio()
187 MMIO_D(DSPPOS(dev_priv, PIPE_B)); in iterate_generic_mmio()
196 MMIO_D(DSPPOS(dev_priv, PIPE_C)); in iterate_generic_mmio()
819 if (!IS_BROXTON(dev_priv)) in iterate_bdw_plus_mmio()
1102 if (IS_KABYLAKE(dev_priv) || in iterate_skl_plus_mmio()
1103 IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) in iterate_skl_plus_mmio()
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/drivers/gpu/drm/gma500/
A Dpsb_drv.c157 psb_spank(dev_priv); in psb_do_init()
186 if (dev_priv->mmu) { in psb_driver_unload()
191 (dev_priv->mmu), in psb_driver_unload()
252 dev_priv->num_pipe = dev_priv->ops->pipes; in psb_driver_load()
256 dev_priv->vdc_reg = in psb_driver_load()
261 dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset, in psb_driver_load()
286 dev_priv->aux_reg = dev_priv->vdc_reg; in psb_driver_load()
289 dev_priv->gmbus_reg = dev_priv->aux_reg; in psb_driver_load()
311 dev_priv->gmbus_reg = dev_priv->vdc_reg; in psb_driver_load()
341 if (!dev_priv->mmu) in psb_driver_load()
[all …]
A Dintel_bios.c55 dev_priv->edp.bpp = 18; in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
84 dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, in parse_edp()
85 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
92 dev_priv->edp.lanes = 1; in parse_edp()
95 dev_priv->edp.lanes = 2; in parse_edp()
99 dev_priv->edp.lanes = 4; in parse_edp()
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
[all …]
A Dpsb_irq.c50 dev_priv->pipestat[pipe] |= mask; in gma_enable_pipestat()
57 gma_power_end(&dev_priv->dev); in gma_enable_pipestat()
66 dev_priv->pipestat[pipe] &= ~mask; in gma_disable_pipestat()
72 gma_power_end(&dev_priv->dev); in gma_disable_pipestat()
91 spin_lock(&dev_priv->irqmask_lock); in gma_pipe_event_handler()
268 if (dev_priv->ops->hotplug) in gma_irq_preinstall()
301 if (dev_priv->ops->hotplug_enable) in gma_irq_postinstall()
315 dev_priv->use_msi = false; in gma_irq_install()
330 dev_priv->irq_enabled = true; in gma_irq_install()
342 if (!dev_priv->irq_enabled) in gma_irq_uninstall()
[all …]
A Dbacklight.c24 dev_priv->backlight_enabled = true; in gma_backlight_enable()
25 dev_priv->ops->backlight_set(dev, dev_priv->backlight_level); in gma_backlight_enable()
32 dev_priv->backlight_enabled = false; in gma_backlight_disable()
40 dev_priv->backlight_level = v; in gma_backlight_set()
41 if (dev_priv->backlight_enabled) in gma_backlight_set()
50 if (dev_priv->ops->backlight_get) in gma_backlight_get_brightness()
53 return dev_priv->backlight_level; in gma_backlight_get_brightness()
81 dev_priv->backlight_level = 100; in gma_backlight_init()
89 dev_priv->ops->backlight_name); in gma_backlight_init()
98 dev_priv->backlight_device = in gma_backlight_init()
[all …]
A Dmid_bios.c54 if (dev_priv->iLVDS_enable) { in mid_get_fuse_settings()
55 dev_priv->is_lvds_on = true; in mid_get_fuse_settings()
56 dev_priv->is_mipi_on = false; in mid_get_fuse_settings()
58 dev_priv->is_mipi_on = true; in mid_get_fuse_settings()
59 dev_priv->is_lvds_on = false; in mid_get_fuse_settings()
74 dev_priv->core_freq = 200; in mid_get_fuse_settings()
77 dev_priv->core_freq = 100; in mid_get_fuse_settings()
80 dev_priv->core_freq = 166; in mid_get_fuse_settings()
85 dev_priv->core_freq = 0; in mid_get_fuse_settings()
109 dev_dbg(dev_priv->dev.dev, "platform_rev_id is %x\n", dev_priv->platform_rev_id); in mid_get_pci_revID()
[all …]
A Dintel_gmbus.c105 struct drm_psb_private *dev_priv = gpio->dev_priv; in get_reserved() local
119 struct drm_psb_private *dev_priv = gpio->dev_priv; in get_clock() local
129 struct drm_psb_private *dev_priv = gpio->dev_priv; in get_data() local
139 struct drm_psb_private *dev_priv = gpio->dev_priv; in set_clock() local
156 struct drm_psb_private *dev_priv = gpio->dev_priv; in set_data() local
193 gpio->dev_priv = dev_priv; in intel_gpio_create()
406 dev_priv->gmbus_reg = dev_priv->aux_reg; in gma_intel_setup_gmbus()
408 dev_priv->gmbus_reg = dev_priv->vdc_reg; in gma_intel_setup_gmbus()
443 kfree(dev_priv->gmbus); in gma_intel_setup_gmbus()
444 dev_priv->gmbus = NULL; in gma_intel_setup_gmbus()
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A Dpower.c51 dev_priv->apm_base = dev_priv->apm_reg & 0xffff; in gma_power_init()
52 dev_priv->ospm_base &= 0xffff; in gma_power_init()
54 if (dev_priv->ops->init_pm) in gma_power_init()
55 dev_priv->ops->init_pm(dev); in gma_power_init()
70 dev_priv->pm_initialized = true; in gma_power_init()
83 if (!dev_priv->pm_initialized) in gma_power_uninit()
99 dev_priv->ops->save_regs(dev); in gma_suspend_display()
100 dev_priv->ops->power_down(dev); in gma_suspend_display()
116 dev_priv->ops->power_up(dev); in gma_resume_display()
142 dev_priv->regs.saveBSM = bsm; in gma_suspend_pci()
[all …]
A Dgtt.c164 iounmap(dev_priv->gtt_map); in psb_gtt_fini()
165 psb_gtt_disable(dev_priv); in psb_gtt_fini()
212 gtt_start = dev_priv->pge_ctl; in psb_gtt_init_ranges()
252 dev_priv->gtt_mem = gtt_mem; in psb_gtt_init_ranges()
267 psb_gtt_init_ranges(dev_priv); in psb_gtt_init()
270 if (!dev_priv->gtt_map) { in psb_gtt_init()
276 psb_gtt_clear(dev_priv); in psb_gtt_init()
281 psb_gtt_disable(dev_priv); in psb_gtt_init()
299 psb_gtt_init_ranges(dev_priv); in psb_gtt_resume()
307 psb_gtt_clear(dev_priv); in psb_gtt_resume()
[all …]
/drivers/gpu/drm/i915/display/
A Di9xx_plane_regs.h12 #define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) argument
15 #define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) argument
49 #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) argument
52 #define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) argument
55 #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) argument
58 #define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) argument
65 #define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) argument
72 #define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) argument
83 #define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) argument
93 #define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) argument
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