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Searched refs:dev_specs (Results 1 – 16 of 16) sorted by relevance

/drivers/net/ethernet/hisilicon/hibmcge/
A Dhbg_txrx.h13 return (dir == HBG_DIR_TX) ? priv->dev_specs.max_frame_len : in hbg_spec_max_frame_len()
14 priv->dev_specs.rx_buf_size; in hbg_spec_max_frame_len()
20 return (dir == HBG_DIR_TX) ? priv->dev_specs.tx_fifo_num : in hbg_get_spec_fifo_max_num()
21 priv->dev_specs.rx_fifo_num; in hbg_get_spec_fifo_max_num()
A Dhbg_main.c338 struct hbg_dev_specs *dev_specs = &priv->dev_specs; in hbg_mac_filter_init() local
342 tmp_table = devm_kcalloc(&priv->pdev->dev, dev_specs->uc_mac_num, in hbg_mac_filter_init()
348 filter->table_max_len = dev_specs->uc_mac_num; in hbg_mac_filter_init()
458 netdev->max_mtu = priv->dev_specs.max_mtu; in hbg_probe()
459 netdev->min_mtu = priv->dev_specs.min_mtu; in hbg_probe()
464 hbg_net_set_mac_address(priv->netdev, &priv->dev_specs.mac_addr); in hbg_probe()
A Dhbg_hw.c64 struct hbg_dev_specs *specs = &priv->dev_specs; in hbg_hw_dev_specs_init()
187 frame_len = mtu + VLAN_HLEN * priv->dev_specs.vlan_layers + in hbg_hw_set_mtu()
350 ctrl |= FIELD_PREP(HBG_REG_RX_CTRL_PORT_NUM, priv->dev_specs.mac_id); in hbg_hw_init_rx_ctrl()
367 HBG_REG_RX_BUF_SIZE_M, priv->dev_specs.rx_buf_size); in hbg_hw_init_rx_control()
A Dhbg_mdio.c107 u32 freq = priv->dev_specs.mdio_frequency; in hbg_mdio_init_hw()
275 mac->phy_addr = priv->dev_specs.phy_addr; in hbg_mdio_init()
A Dhbg_common.h268 struct hbg_dev_specs dev_specs; member
A Dhbg_txrx.c345 priv->dev_specs.max_frame_len)) { in hbg_rx_pkt_check()
351 priv->dev_specs.mac_id || in hbg_rx_pkt_check()
/drivers/net/ethernet/hisilicon/hns3/
A Dhns3_debugfs.c731 struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; in hns3_dbg_dev_specs() local
736 seq_printf(s, "MAC entry num: %u\n", dev_specs->mac_entry_num); in hns3_dbg_dev_specs()
737 seq_printf(s, "MNG entry num: %u\n", dev_specs->mng_entry_num); in hns3_dbg_dev_specs()
739 dev_specs->max_non_tso_bd_num); in hns3_dbg_dev_specs()
741 seq_printf(s, "RSS key size: %u\n", dev_specs->rss_key_size); in hns3_dbg_dev_specs()
750 seq_printf(s, "MAX INT QL: %u\n", dev_specs->int_ql_max); in hns3_dbg_dev_specs()
751 seq_printf(s, "MAX INT GL: %u\n", dev_specs->max_int_gl); in hns3_dbg_dev_specs()
752 seq_printf(s, "MAX TM RATE: %u\n", dev_specs->max_tm_rate); in hns3_dbg_dev_specs()
754 seq_printf(s, "umv size: %u\n", dev_specs->umv_size); in hns3_dbg_dev_specs()
755 seq_printf(s, "mc mac size: %u\n", dev_specs->mc_mac_size); in hns3_dbg_dev_specs()
[all …]
A Dhns3_ethtool.c937 return ae_dev->dev_specs.rss_ind_tbl_size; in hns3_get_rss_indir_size()
1396 if (cmd->rx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) { in hns3_check_gl_coalesce_para()
1399 ae_dev->dev_specs.max_int_gl); in hns3_check_gl_coalesce_para()
1403 if (cmd->tx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) { in hns3_check_gl_coalesce_para()
1406 ae_dev->dev_specs.max_int_gl); in hns3_check_gl_coalesce_para()
1468 !ae_dev->dev_specs.int_ql_max) { in hns3_check_ql_coalesce_param()
1473 if (cmd->tx_max_coalesced_frames > ae_dev->dev_specs.int_ql_max || in hns3_check_ql_coalesce_param()
1474 cmd->rx_max_coalesced_frames > ae_dev->dev_specs.int_ql_max) { in hns3_check_ql_coalesce_param()
1477 ae_dev->dev_specs.int_ql_max); in hns3_check_ql_coalesce_param()
A Dhnae3.h437 struct hnae3_dev_specs dev_specs; member
A Dhns3_enet.c574 if (ae_dev->dev_specs.int_ql_max) { in hns3_vector_coalesce_init()
577 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; in hns3_vector_coalesce_init()
578 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; in hns3_vector_coalesce_init()
4774 if (ae_dev->dev_specs.int_ql_max) { in hns3_nic_init_coal_cfg()
5344 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; in hns3_client_init()
5427 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); in hns3_client_init()
/drivers/net/ethernet/hisilicon/hns3/hns3vf/
A Dhclgevf_main.c580 hdev->ae_dev->dev_specs.rss_ind_tbl_size); in hclgevf_get_rss()
2732 ae_dev->dev_specs.max_non_tso_bd_num = in hclgevf_set_default_dev_specs()
2751 ae_dev->dev_specs.rss_ind_tbl_size = in hclgevf_parse_dev_specs()
2761 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; in hclgevf_check_dev_specs() local
2763 if (!dev_specs->max_non_tso_bd_num) in hclgevf_check_dev_specs()
2765 if (!dev_specs->rss_ind_tbl_size) in hclgevf_check_dev_specs()
2767 if (!dev_specs->rss_key_size) in hclgevf_check_dev_specs()
2769 if (!dev_specs->max_int_gl) in hclgevf_check_dev_specs()
2770 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; in hclgevf_check_dev_specs()
2771 if (!dev_specs->max_frm_size) in hclgevf_check_dev_specs()
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/drivers/net/ethernet/hisilicon/hns3/hns3_common/
A Dhclge_comm_rss.c38 u16 rss_ind_tbl_size = ae_dev->dev_specs.rss_ind_tbl_size; in hclge_comm_rss_init_cfg()
223 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) in hclge_comm_rss_indir_init_cfg()
288 rss_cfg_tbl_num = ae_dev->dev_specs.rss_ind_tbl_size / in hclge_comm_set_rss_indir_table()
/drivers/net/ethernet/hisilicon/hns3/hns3pf/
A Dhclge_main.c1376 ae_dev->dev_specs.tnl_num = 0; in hclge_set_default_dev_specs()
1390 ae_dev->dev_specs.rss_ind_tbl_size = in hclge_parse_dev_specs()
1406 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; in hclge_check_dev_specs() local
1408 if (!dev_specs->max_non_tso_bd_num) in hclge_check_dev_specs()
1410 if (!dev_specs->rss_ind_tbl_size) in hclge_check_dev_specs()
1412 if (!dev_specs->rss_key_size) in hclge_check_dev_specs()
1414 if (!dev_specs->max_tm_rate) in hclge_check_dev_specs()
1416 if (!dev_specs->max_qset_num) in hclge_check_dev_specs()
1418 if (!dev_specs->max_int_gl) in hclge_check_dev_specs()
1420 if (!dev_specs->max_frm_size) in hclge_check_dev_specs()
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A Dhclge_tm.c474 hdev->ae_dev->dev_specs.max_tm_rate); in hclge_tm_port_shaper_cfg()
598 max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_qs_shaper_cfg()
602 hdev->ae_dev->dev_specs.max_tm_rate); in hclge_tm_qs_shaper_cfg()
801 hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_pg_info_init()
885 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_pg_shaper_cfg()
1047 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_pri_tc_base_shaper_cfg()
1098 hdev->ae_dev->dev_specs.max_tm_rate); in hclge_tm_pri_vnet_base_shaper_pri_cfg()
1128 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; in hclge_tm_pri_vnet_base_shaper_qs_cfg()
A Dhclge_regs.c419 HCLGE_REG_TLV_SIZE) * ae_dev->dev_specs.tnl_num; in hclge_get_dfx_reg_len()
434 for (i = HCLGE_REG_RPU_TNL_ID_0; i <= ae_dev->dev_specs.tnl_num; i++) { in hclge_get_dfx_rpu_tnl_reg()
A Dhclge_err.c1611 loop_time = min(hdev->ae_dev->dev_specs.tnl_num, in hclge_query_reg_info_of_ssu()

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