| /drivers/clk/ |
| A D | clk-fixed-rate.c | 69 unsigned long clk_fixed_flags, bool devm) in __clk_hw_register_fixed_rate() argument
77 if (devm) in __clk_hw_register_fixed_rate()
109 if (devm) in __clk_hw_register_fixed_rate()
114 } else if (devm) in __clk_hw_register_fixed_rate()
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| A D | clk-fixed-factor.c | 96 unsigned long acc, unsigned int fixflags, bool devm) in __clk_hw_register_fixed_factor() argument
104 if (devm && !dev) in __clk_hw_register_fixed_factor()
107 if (devm) in __clk_hw_register_fixed_factor()
139 if (devm) in __clk_hw_register_fixed_factor()
144 } else if (devm) in __clk_hw_register_fixed_factor()
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| /drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| A D | chan.h | 41 int (*write)(struct nvkm_chan *, u64 offset, u64 length, u32 devm, bool priv);
44 u32 devm; member
57 const char *name, bool priv, u32 devm, struct nvkm_vmm *, struct nvkm_dmaobj *,
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| A D | chan.c | 346 struct nvkm_cgrp *cgrp, const char *name, bool priv, u32 devm, struct nvkm_vmm *vmm, in nvkm_chan_new_() argument
360 ((func->ramfc->devm < devm) && devm != BIT(0)) || in nvkm_chan_new_()
366 func->ramfc->devm, devm, func->ramfc->priv, priv); in nvkm_chan_new_()
475 ret = chan->func->ramfc->write(chan, offset, length, devm, priv); in nvkm_chan_new_()
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| A D | g84.c | 43 g84_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in g84_chan_ramfc_write() argument
77 nvkm_wo32(chan->ramfc, 0x7c, 0x30000000 | devm); in g84_chan_ramfc_write()
91 .devm = 0xfff,
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| A D | gv100.c | 41 gv100_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in gv100_chan_ramfc_write() argument
54 nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm); in gv100_chan_ramfc_write()
67 .devm = 0xfff,
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| A D | nv50.c | 80 nv50_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in nv50_chan_ramfc_write() argument
110 nvkm_wo32(chan->ramfc, 0x7c, 0x30000000 | devm); in nv50_chan_ramfc_write()
122 .devm = 0xfff,
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| A D | nv10.c | 37 nv10_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in nv10_chan_ramfc_write() argument
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| A D | ga100.c | 70 ga100_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in ga100_chan_ramfc_write() argument
80 nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm); in ga100_chan_ramfc_write()
93 .devm = 0xfff,
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| A D | gk104.c | 82 gk104_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in gk104_chan_ramfc_write() argument
95 nvkm_wo32(chan->inst, 0x94, 0x30000000 | devm); in gk104_chan_ramfc_write()
110 .devm = 0xfff,
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| A D | nv17.c | 38 nv17_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in nv17_chan_ramfc_write() argument
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| A D | nv40.c | 39 nv40_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in nv40_chan_ramfc_write() argument
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| A D | gf100.c | 85 gf100_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in gf100_chan_ramfc_write() argument
99 nvkm_wo32(chan->inst, 0x94, 0x30000000 | devm); in gf100_chan_ramfc_write()
114 .devm = 0xfff,
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| A D | uchan.c | 387 args->v0.priv != 0, args->v0.devm, vmm, ctxdma, args->v0.offset, in nvkm_uchan_new()
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| A D | nv04.c | 116 nv04_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in nv04_chan_ramfc_write() argument
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| /drivers/gpu/drm/nouveau/include/nvif/ |
| A D | if0020.h | 13 __u16 devm; member
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| /drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ |
| A D | fifo.c | 154 r535_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) in r535_chan_ramfc_write() argument
225 .devm = 0xfff,
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| /drivers/gpu/drm/nouveau/ |
| A D | nouveau_chan.c | 302 args->devm = BIT(0); in nouveau_channel_ctor()
|