| /drivers/gpu/drm/omapdrm/dss/ |
| A D | dispc.c | 3150 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; in dispc_mgr_set_lcd_divisor() 3796 dispc->core_clk_rate = dispc_fclk_rate(dispc); in _omap_dispc_initial_config() 4372 return dispc->user_handler(irq, dispc->user_data); in dispc_irq_handler() 4401 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); in dispc_free_irq() 4606 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL); in dispc_bind() 4607 if (!dispc) in dispc_bind() 4634 dispc->irq = platform_get_irq(dispc->pdev, 0); in dispc_bind() 4675 dss->dispc = dispc; in dispc_bind() 4678 dispc); in dispc_bind() 4685 kfree(dispc); in dispc_bind() [all …]
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| A D | dss.h | 259 struct dispc_device *dispc; member 391 int dispc_runtime_get(struct dispc_device *dispc); 392 void dispc_runtime_put(struct dispc_device *dispc); 394 int dispc_get_num_ovls(struct dispc_device *dispc); 395 int dispc_get_num_mgrs(struct dispc_device *dispc); 422 void dispc_mgr_enable(struct dispc_device *dispc, 425 bool dispc_mgr_go_busy(struct dispc_device *dispc, 436 void dispc_mgr_setup(struct dispc_device *dispc, 444 u32 dispc_mgr_gamma_size(struct dispc_device *dispc, 451 int dispc_ovl_setup(struct dispc_device *dispc, [all …]
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| A D | dpi.c | 179 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dpi_calc_hsdiv_cb() argument 185 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; in dpi_calc_hsdiv_cb() 187 return dispc_div_calc(ctx->dpi->dss->dispc, dispc, in dpi_calc_hsdiv_cb() 215 return dispc_div_calc(ctx->dpi->dss->dispc, fck, in dpi_calc_dss_cb() 496 r = dispc_runtime_get(dpi->dss->dispc); in dpi_bridge_enable() 530 dispc_runtime_put(dpi->dss->dispc); in dpi_bridge_enable() 548 dispc_runtime_put(dpi->dss->dispc); in dpi_bridge_disable()
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| A D | sdi.c | 69 return dispc_div_calc(ctx->sdi->dss->dispc, fck, in dpi_calc_dss_cb() 211 r = dispc_runtime_get(sdi->dss->dispc); in sdi_bridge_enable() 238 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, in sdi_bridge_enable() 258 dispc_runtime_put(sdi->dss->dispc); in sdi_bridge_enable() 271 dispc_runtime_put(sdi->dss->dispc); in sdi_bridge_disable()
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| A D | dss.c | 267 dispc_pck_free_enable(dss->dispc, 1); in dss_sdi_enable() 297 dispc_lcd_enable_signal(dss->dispc, 1); in dss_sdi_enable() 311 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_enable() 316 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_enable() 323 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_disable() 325 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_disable() 386 dispc_dump_clocks(dss->dispc, s); in dss_debug_dump_clocks()
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| A D | dsi.c | 934 dispc_pck_free_enable(dsi->dss->dispc, 1); in dsi_pll_enable() 939 dispc_pck_free_enable(dsi->dss->dispc, 0); in dsi_pll_enable() 945 dispc_pck_free_enable(dsi->dss->dispc, 0); in dsi_pll_enable() 3145 dispc_disable_sidle(dsi->dss->dispc); in dsi_update_screen_dispc() 3178 dispc_enable_sidle(dsi->dss->dispc); in dsi_handle_framedone() 3316 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); in dsi_configure_dispc_clocks() 3682 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dsi_cm_calc_hsdiv_cb() argument 3688 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; in dsi_cm_calc_hsdiv_cb() 3690 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, in dsi_cm_calc_hsdiv_cb() 3978 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; in dsi_vm_calc_hsdiv_cb() [all …]
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| A D | base.c | 21 return dss->dispc; in dispc_get_dispc()
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| /drivers/gpu/drm/tidss/ |
| A D | tidss_dispc.c | 625 dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, in REG_FLD_MOD() 652 dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), in VP_REG_FLD_MOD() 925 dispc_write(dispc, DISPC_IRQSTATUS, dispc_read(dispc, DISPC_IRQSTATUS)); in dispc_k3_clear_irqstatus() 1979 dev_dbg(dispc->dev, in dispc_vid_calc_scaling() 2362 dev_dbg(dispc->dev, in dispc_k2g_plane_init() 2417 dev_dbg(dispc->dev, in dispc_k3_plane_init() 3005 dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL); in dispc_init() 3006 if (!dispc) in dispc_init() 3010 dispc->dev = dev; in dispc_init() 3011 dispc->feat = feat; in dispc_init() [all …]
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| A D | tidss_dispc.h | 112 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, 114 void dispc_ovr_enable_layer(struct dispc_device *dispc, 117 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, 119 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, 121 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport); 124 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport); 134 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, 137 int dispc_runtime_suspend(struct dispc_device *dispc); 138 int dispc_runtime_resume(struct dispc_device *dispc); 140 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, [all …]
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| A D | tidss_crtc.c | 37 busy = dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_finish_page_flip() 91 struct dispc_device *dispc = tidss->dispc; in tidss_crtc_atomic_check() local 104 ok = dispc_vp_mode_valid(dispc, hw_videoport, mode); in tidss_crtc_atomic_check() 111 return dispc_vp_bus_check(dispc, hw_videoport, crtc_state); in tidss_crtc_atomic_check() 152 dispc_ovr_set_plane(tidss->dispc, tplane->hw_plane_id, in tidss_crtc_position_planes() 201 dispc_vp_go(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_atomic_flush() 227 r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport, in tidss_crtc_atomic_enable() 232 r = dispc_vp_enable_clk(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_atomic_enable() 278 dispc_vp_disable(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_atomic_disable() 285 dispc_vp_unprepare(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_atomic_disable() [all …]
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| A D | tidss_drv.c | 60 return dispc_runtime_suspend(tidss->dispc); in tidss_pm_runtime_suspend() 70 r = dispc_runtime_resume(tidss->dispc); in tidss_pm_runtime_resume() 162 dispc_runtime_resume(tidss->dispc); in tidss_probe() 206 dispc_runtime_suspend(tidss->dispc); in tidss_probe() 232 dispc_runtime_suspend(tidss->dispc); in tidss_remove()
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| A D | tidss_plane.c | 109 ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state, in tidss_plane_atomic_check() 130 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_update() 136 dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, new_state, hw_videoport); in tidss_plane_atomic_update() 148 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true); in tidss_plane_atomic_enable() 160 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_disable()
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| A D | tidss_irq.c | 22 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update() 63 irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_handler()
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| A D | tidss_drv.h | 24 struct dispc_device *dispc; member
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| /drivers/gpu/drm/omapdrm/ |
| A D | omap_irq.c | 32 dispc_write_irqenable(priv->dispc, irqmask); in omap_irq_update() 86 dispc_mgr_get_framedone_irq(priv->dispc, channel); in omap_irq_enable_framedone() 123 priv->irq_mask |= dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank() 149 priv->irq_mask &= ~dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank() 214 irqstatus = dispc_read_irqstatus(priv->dispc); in omap_irq_handler() 215 dispc_clear_irqstatus(priv->dispc, irqstatus); in omap_irq_handler() 259 unsigned int num_mgrs = dispc_get_num_mgrs(priv->dispc); in omap_drm_irq_install() 279 dispc_runtime_get(priv->dispc); in omap_drm_irq_install() 280 dispc_clear_irqstatus(priv->dispc, 0xffffffff); in omap_drm_irq_install() 281 dispc_runtime_put(priv->dispc); in omap_drm_irq_install() [all …]
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| A D | omap_crtc.c | 105 dispc_mgr_enable(priv->dispc, channel, true); in omap_crtc_dss_start_update() 130 dispc_mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled() 143 framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc, in omap_crtc_set_enabled() 165 dispc_mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled() 187 dispc_mgr_set_timings(priv->dispc, omap_crtc->channel, in omap_crtc_dss_enable() 457 dispc_runtime_get(priv->dispc); in omap_crtc_atomic_enable() 496 dispc_runtime_put(priv->dispc); in omap_crtc_atomic_disable() 515 r = dispc_mgr_check_timings(priv->dispc, in omap_crtc_mode_valid() 633 dispc_mgr_set_gamma(priv->dispc, omap_crtc->channel, in omap_crtc_atomic_flush() 658 dispc_mgr_go(priv->dispc, omap_crtc->channel); in omap_crtc_atomic_flush() [all …]
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| A D | omap_plane.c | 140 ret = dispc_ovl_setup(priv->dispc, ovl_id, &info, in omap_plane_atomic_update() 146 dispc_ovl_enable(priv->dispc, ovl_id, false); in omap_plane_atomic_update() 150 dispc_ovl_enable(priv->dispc, ovl_id, true); in omap_plane_atomic_update() 153 ret = dispc_ovl_setup(priv->dispc, r_ovl_id, &r_info, in omap_plane_atomic_update() 159 dispc_ovl_enable(priv->dispc, r_ovl_id, false); in omap_plane_atomic_update() 160 dispc_ovl_enable(priv->dispc, ovl_id, false); in omap_plane_atomic_update() 164 dispc_ovl_enable(priv->dispc, r_ovl_id, true); in omap_plane_atomic_update() 224 dispc_ovl_get_max_size(priv->dispc, &width, &height); in omap_plane_atomic_check() 316 if (!dispc_ovl_color_mode_supported(priv->dispc, omap_state->overlay->id, in omap_plane_atomic_check() 524 unsigned int num_planes = dispc_get_num_ovls(priv->dispc); in omap_plane_init() [all …]
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| A D | omap_overlay.c | 50 if (!dispc_ovl_color_mode_supported(priv->dispc, in omap_plane_find_free_overlay() 147 dispc_ovl_enable(priv->dispc, overlay->id, false); in omap_overlay_update_state() 178 u32 num_overlays = dispc_get_num_ovls(priv->dispc); in omap_hwoverlays_init() 185 caps = dispc_ovl_get_caps(priv->dispc, hw_plane_ids[i]); in omap_hwoverlays_init()
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| A D | omap_drv.c | 72 dispc_runtime_get(priv->dispc); in omap_atomic_commit_tail() 116 dispc_runtime_put(priv->dispc); in omap_atomic_commit_tail() 366 unsigned int num_planes = dispc_get_num_ovls(priv->dispc); in omap_modeset_init_properties() 395 int num_ovls = dispc_get_num_ovls(priv->dispc); in omap_modeset_init() 396 int num_mgrs = dispc_get_num_mgrs(priv->dispc); in omap_modeset_init() 690 priv->dispc = dispc_get_dispc(priv->dss); in omapdrm_init() 706 priv->max_bandwidth = dispc_get_memory_bandwidth_limit(priv->dispc); in omapdrm_init()
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| A D | omap_drv.h | 64 struct dispc_device *dispc; member
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| A D | Makefile | 22 omapdrm-y += dss/base.o dss/output.o dss/dss.o dss/dispc.o \
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| A D | dispc.c | 127 } dispc; variable 400 if (!dispc.ctx_valid) in dispc_restore_context() 3114 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, in _dispc_mgr_set_lcd_timings() 3608 lck = dispc / lckd; in dispc_div_calc() 3863 return dispc.user_handler(irq, dispc.user_data); in dispc_irq_handler() 3879 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, in dispc_request_irq() 3892 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); in dispc_free_irq() 3908 dispc.pdev = pdev; in dispc_bind() 3913 if (!dispc.feat) in dispc_bind() 3924 if (!dispc.base) { in dispc_bind() [all …]
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| A D | Makefile | 5 omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \ 9 dispc-compat.o display-sysfs.o
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| A D | dpi.c | 172 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dpi_calc_hsdiv_cb() argument 186 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; in dpi_calc_hsdiv_cb() 188 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max, in dpi_calc_hsdiv_cb()
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| A D | dss.h | 373 bool dispc_div_calc(unsigned long dispc, 456 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
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