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Searched refs:display (Results 1 – 25 of 452) sorted by relevance

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/drivers/gpu/drm/i915/display/
A Dintel_display_driver.c88 if (!HAS_DISPLAY(display)) in intel_display_driver_init_hw()
147 if (display->platform.i845g || display->platform.i865g) { in intel_mode_config_init()
150 } else if (display->platform.i830 || display->platform.i85x || in intel_mode_config_init()
151 display->platform.i915g || display->platform.i915gm) { in intel_mode_config_init()
254 if (!display->wq.flip) { in intel_display_driver_probe_noirq()
271 intel_dmc_init(display); in intel_display_driver_probe_noirq()
297 intel_fbc_init(display); in intel_display_driver_probe_noirq()
462 intel_wm_init(display); in intel_display_driver_probe_nogem()
502 intel_modeset_setup_hw_state(display, display->drm->mode_config.acquire_ctx); in intel_display_driver_probe_nogem()
513 if (!HAS_GMCH(display)) in intel_display_driver_probe_nogem()
[all …]
A Dintel_pch.c54 else if (display->platform.battlemage || display->platform.meteorlake) in intel_pch_fake_for_south_display()
71 drm_WARN_ON(display->drm, DISPLAY_VER(display) != 5); in intel_pch_type()
180 drm_WARN_ON(display->drm, !display->platform.icelake); in intel_pch_type()
184 drm_WARN_ON(display->drm, !(display->platform.jasperlake || in intel_pch_type()
191 drm_WARN_ON(display->drm, !display->platform.tigerlake && in intel_pch_type()
200 drm_WARN_ON(display->drm, !(display->platform.jasperlake || in intel_pch_type()
209 drm_WARN_ON(display->drm, !display->platform.alderlake_s && in intel_pch_type()
240 if (display->platform.alderlake_s || display->platform.alderlake_p) in intel_virt_detect_pch()
251 else if (display->platform.kabylake || display->platform.skylake) in intel_virt_detect_pch()
256 else if (display->platform.haswell || display->platform.broadwell) in intel_virt_detect_pch()
[all …]
A Dintel_display_irq.c378 return IS_DISPLAY_VER(display, 3, 4) && display->platform.mobile; in i915_has_legacy_blc_interrupt()
488 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in i9xx_pipe_crc_irq_handler()
494 intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)), in i9xx_pipe_crc_irq_handler()
1328 drm_WARN_ON(display->drm, INTEL_PCH_TYPE(display) < PCH_MTL); in gen8_read_and_ack_pch_irqs()
1346 drm_WARN_ON_ONCE(display->drm, !HAS_DISPLAY(display)); in gen8_de_irq_handler()
1471 if (HAS_PCH_SPLIT(display) && !HAS_PCH_NOP(display) && in gen8_de_irq_handler()
1875 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); in _vlv_display_irq_reset()
1895 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); in i9xx_display_irq_reset()
2138 else if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display)) in ibx_irq_postinstall()
2215 if (display->platform.ironlake && display->platform.mobile) in ilk_de_irq_postinstall()
[all …]
A Dintel_display_power_well.c432 drm_WARN_ON(display->drm, !display->platform.icelake); in icl_combo_phy_aux_power_well_enable()
459 drm_WARN_ON(display->drm, !display->platform.icelake); in icl_combo_phy_aux_power_well_disable()
616 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && in hsw_power_well_enabled()
858 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) in gen9_enable_dc5()
889 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) in skl_enable_dc6()
907 if (display->platform.broxton || display->platform.geminilake) in bxt_enable_dc9()
1211 intel_de_rmw(display, DSPCLK_GATE_D(display), in vlv_init_display_clock_gating()
1241 u32 val = intel_de_read(display, DPLL(display, pipe)); in vlv_display_power_well_init()
1247 intel_de_write(display, DPLL(display, pipe), val); in vlv_display_power_well_init()
1853 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), in xelpdp_aux_power_well_enable()
[all …]
A Dintel_display_power.c964 else if (display->platform.geminilake || display->platform.broxton) in get_allowed_dc_mask()
1031 get_allowed_dc_mask(display, display->params.enable_dc); in intel_power_domains_init()
1155 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) in icl_mbus_init()
1221 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, in assert_can_disable_lcpll()
1452 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); in skl_display_core_init()
1614 if (display->platform.dgfx && !display->platform.dg1) in tgl_bw_buddy_init()
1664 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); in icl_display_core_init()
1688 if (DISPLAY_VER(display) == 12 || display->platform.dg2) in icl_display_core_init()
1797 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); in chv_phy_control_init()
1957 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); in intel_power_domains_init_hw()
[all …]
A Dintel_hotplug_irq.c142 if (display->platform.g4x || display->platform.valleyview || in intel_hpd_init_pins()
154 else if (display->platform.geminilake || display->platform.broxton) in intel_hpd_init_pins()
166 (!HAS_PCH_SPLIT(display) || HAS_PCH_NOP(display))) in intel_hpd_init_pins()
175 else if (HAS_PCH_CNP(display) || HAS_PCH_SPT(display)) in intel_hpd_init_pins()
177 else if (HAS_PCH_LPT(display) || HAS_PCH_CPT(display)) in intel_hpd_init_pins()
192 intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits); in i915_hotplug_interrupt_update_locked()
424 display->platform.valleyview || display->platform.cherryview) in i9xx_hpd_irq_ack()
447 intel_de_write(display, PORT_HOTPLUG_STAT(display), in i9xx_hpd_irq_ack()
453 intel_de_read(display, PORT_HOTPLUG_STAT(display))); in i9xx_hpd_irq_ack()
464 display->platform.valleyview || display->platform.cherryview) in i9xx_hpd_irq_handler()
[all …]
A Di9xx_display_sr.c22 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
23 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
26 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
29 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
32 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
33 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
36 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
47 intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); in i9xx_display_restore_swf()
48 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
51 intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); in i9xx_display_restore_swf()
[all …]
A Dintel_fdi.c34 if (HAS_DDI(display)) { in assert_fdi_tx()
92 if (HAS_DDI(display)) in assert_fdi_tx_pll_enabled()
147 if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3) in intel_fdi_add_affected_crtcs()
195 drm_dbg_kms(display->drm, in ilk_check_fdi_lanes()
205 if (display->platform.haswell || display->platform.broadwell) { in ilk_check_fdi_lanes()
277 } else if (display->platform.sandybridge || display->platform.ivybridge) { in intel_fdi_pll_freq_update()
283 drm_dbg(display->drm, "FDI PLL freq=%d\n", display->fdi.pll_freq); in intel_fdi_pll_freq_update()
289 if (HAS_DDI(display)) in intel_fdi_link_freq()
519 intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK); in ilk_fdi_link_train()
620 intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK); in gen6_fdi_link_train()
[all …]
A Dintel_fifo_underrun.c67 for_each_pipe(display, pipe) { in ivb_can_enable_err_int()
84 for_each_pipe(display, pipe) { in cpt_can_enable_serr_int()
124 intel_de_write(display, reg, in i9xx_set_fifo_underrun_reporting()
181 drm_err(display->drm, in ivb_set_fifo_underrun_reporting()
247 drm_err(display->drm, in cpt_set_fifo_underrun_reporting()
265 if (HAS_GMCH(display)) in __intel_set_cpu_fifo_underrun_reporting()
267 else if (display->platform.ironlake || display->platform.sandybridge) in __intel_set_cpu_fifo_underrun_reporting()
342 if (HAS_PCH_IBX(display)) in intel_set_pch_fifo_underrun_reporting()
374 if (HAS_GMCH(display) && in intel_cpu_fifo_underrun_irq_handler()
426 if (HAS_GMCH(display)) in intel_check_cpu_fifo_underruns()
[all …]
A Dintel_hotplug.c173 drm_dbg_kms(display->drm, in intel_hpd_irq_storm_detect()
247 drm_info(display->drm, in intel_hpd_irq_storm_switch_to_polling()
289 drm_dbg(display->drm, in intel_hpd_irq_storm_reenable_work()
619 drm_dbg(display->drm, in intel_hpd_irq_handler()
650 drm_WARN_ONCE(display->drm, !HAS_GMCH(display), in intel_hpd_irq_handler()
695 queue_work(display->hotplug.dp_wq, &display->hotplug.dig_port_work); in intel_hpd_irq_handler()
866 if (!HAS_DISPLAY(display) || !intel_display_device_enabled(display)) in intel_hpd_poll_enable()
950 display->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(display); in intel_hpd_init_early()
974 drm_WARN_ON(display->drm, get_blocked_hpd_pin_mask(display)); in intel_hpd_cancel_work()
1023 queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0); in queue_work_for_missed_irqs()
[all …]
A Dintel_cdclk.c166 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
173 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
372 tmp = intel_de_read(display, display->platform.pineview || in intel_hpll_vco()
1246 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in skl_sanitize_cdclk()
2170 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) in bxt_set_cdclk()
2252 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in bxt_sanitize_cdclk()
2256 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
3235 intel_atomic_global_obj_init(display, &display->cdclk.obj, in intel_cdclk_init()
3481 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; in intel_update_max_cdclk()
3501 intel_cdclk_get_cdclk(display, &display->cdclk.hw); in intel_update_cdclk()
[all …]
A Dintel_gmbus.c212 intel_de_write(display, GMBUS0(display), 0); in intel_gmbus_reset()
213 intel_de_write(display, GMBUS4(display), 0); in intel_gmbus_reset()
220 intel_de_rmw(display, DSPCLK_GATE_D(display), in pnv_gmbus_clock_gating()
242 struct intel_display *display = bus->display; in get_reserved() local
256 struct intel_display *display = bus->display; in get_clock() local
268 struct intel_display *display = bus->display; in get_data() local
280 struct intel_display *display = bus->display; in set_clock() local
297 struct intel_display *display = bus->display; in set_data() local
455 intel_de_write_fw(display, GMBUS1(display), in gmbus_xfer_read_chunk()
534 intel_de_write_fw(display, GMBUS1(display), in gmbus_xfer_write_chunk()
[all …]
A Dintel_pch_refclk.c38 lpt_fdi_reset_mphy(display); in lpt_fdi_program_mphy()
116 intel_sbi_lock(display); in lpt_disable_iclkip()
122 intel_sbi_unlock(display); in lpt_disable_iclkip()
198 drm_dbg_kms(display->drm, in lpt_program_iclkip()
202 intel_sbi_lock(display); in lpt_program_iclkip()
243 intel_sbi_lock(display); in lpt_get_iclkip()
282 if (drm_WARN(display->drm, HAS_PCH_LPT_LP(display) && in lpt_enable_clkout_dp()
286 intel_sbi_lock(display); in lpt_enable_clkout_dp()
317 intel_sbi_lock(display); in lpt_disable_clkout_dp()
429 if ((display->platform.broadwell || display->platform.haswell_ult) && in wrpll_uses_pch_ssc()
[all …]
A Dintel_dmc.c929 struct intel_display *display = dmc->display; in dmc_set_fw_offset() local
959 struct intel_display *display = dmc->display; in dmc_mmio_addr_sanity_check() local
992 struct intel_display *display = dmc->display; in parse_dmc_fw_header() local
1111 struct intel_display *display = dmc->display; in parse_dmc_fw_package() local
1165 struct intel_display *display = dmc->display; in parse_dmc_fw_css() local
1187 struct intel_display *display = dmc->display; in parse_dmc_fw() local
1240 drm_WARN_ON(display->drm, display->dmc.wakeref); in intel_dmc_runtime_pm_get()
1263 struct intel_display *display = dmc->display; in dmc_load_work_fn() local
1337 dmc->display = display; in intel_dmc_init()
1438 drm_WARN_ON(display->drm, display->dmc.wakeref); in intel_dmc_fini()
[all …]
A Dintel_pch_display.c28 return HAS_PCH_IBX(display) || HAS_PCH_CPT(display) || in intel_has_pch_trancoder()
36 if (HAS_PCH_LPT(display)) in intel_crtc_pch_transcoder()
230 intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
232 intel_de_read(display, TRANS_HBLANK(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
234 intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
237 intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
239 intel_de_read(display, TRANS_VBLANK(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
241 intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
243 intel_de_read(display, TRANS_VSYNCSHIFT(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
277 pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe)); in ilk_enable_pch_transcoder()
[all …]
A Dvlv_dsi.c175 intel_de_write(display, MIPI_INTR_STAT(display, port), in intel_dsi_host_transfer()
349 intel_de_rmw(display, MIPI_CTRL(display, port), in glk_dsi_enable_io()
388 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
393 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
517 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_enter_low_power_mode()
624 intel_de_rmw(display, MIPI_CTRL(display, port), in intel_dsi_port_enable()
764 intel_de_rmw(display, DSPCLK_GATE_D(display), in intel_dsi_pre_enable()
921 intel_de_rmw(display, DSPCLK_GATE_D(display), in intel_dsi_post_disable()
1333 intel_de_write(display, MIPI_CTRL(display, PORT_A), in intel_dsi_prepare()
1339 intel_de_write(display, MIPI_CTRL(display, port), in intel_dsi_prepare()
[all …]
A Dintel_combo_phy.c101 drm_dbg_kms(display->drm, in check_phy_reg()
143 else if ((display->platform.jasperlake || display->platform.elkhartlake) || in has_phy_misc()
145 display->platform.dg1) in has_phy_misc()
184 drm_err(display->drm, in ehl_vbt_ddi_d_present()
212 else if (display->platform.dg1 || display->platform.rocketlake) in phy_is_master()
244 if (display->platform.jasperlake || display->platform.elkhartlake) { in icl_combo_phy_verify_state()
322 drm_dbg_kms(display->drm, in icl_combo_phys_init()
338 if ((display->platform.jasperlake || display->platform.elkhartlake) && in icl_combo_phys_init()
382 if (display->platform.tigerlake || display->platform.dg1) { in icl_combo_phys_uninit()
388 drm_dbg_kms(display->drm, in icl_combo_phys_uninit()
[all …]
A Di9xx_plane.c122 if (display->platform.broadwell || display->platform.haswell) in i9xx_plane_has_fbc()
149 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in i9xx_plane_has_windowing()
168 if (display->platform.g4x || display->platform.ironlake || in i9xx_plane_ctl()
450 intel_de_write_fw(display, DSPPOS(display, i9xx_plane), in i9xx_plane_update_noarm()
452 intel_de_write_fw(display, DSPSIZE(display, i9xx_plane), in i9xx_plane_update_noarm()
488 intel_de_write_fw(display, PRIMPOS(display, i9xx_plane), in i9xx_plane_update_arm()
514 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), in i9xx_plane_update_arm()
615 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), in g4x_primary_async_flip()
950 if (HAS_FBC(display) && DISPLAY_VER(display) < 4 && in intel_primary_plane_create()
1040 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_primary_plane_create()
[all …]
A Dintel_wm.c53 display->funcs.wm->update_wm(display); in intel_update_watermarks()
111 return display->funcs.wm->get_hw_state(display); in intel_wm_get_hw_state()
117 return display->funcs.wm->sanitize(display); in intel_wm_sanitize()
152 drm_dbg_kms(display->drm, in intel_print_wm_latency()
167 drm_dbg_kms(display->drm, in intel_print_wm_latency()
176 skl_wm_init(display); in intel_wm_init()
178 i9xx_wm_init(display); in intel_wm_init()
198 display->platform.g4x) in wm_latency_show()
259 if (DISPLAY_VER(display) < 5 && !display->platform.g4x) in pri_wm_latency_open()
269 if (HAS_GMCH(display)) in spr_wm_latency_open()
[all …]
A Dintel_flipq.c118 if (!display->dmc.dmc) in intel_flipq_supported()
121 if (DISPLAY_VER(display) == 20) in intel_flipq_supported()
125 return DISPLAY_VER(display) >= 30 && intel_vrr_always_use_vrr_tg(display); in intel_flipq_supported()
140 if (DISPLAY_VER(display) >= 30) in cdclk_factor()
149 DIV_ROUND_UP(display->cdclk.hw.cdclk * cdclk_factor(display), 540000) + in intel_flipq_exec_time_us()
150 display->sagv.block_time_us; in intel_flipq_exec_time_us()
215 drm_dbg_kms(display->drm, in intel_flipq_dump()
226 drm_dbg_kms(display->drm, in intel_flipq_dump()
232 drm_dbg_kms(display->drm, in intel_flipq_dump()
237 drm_dbg_kms(display->drm, in intel_flipq_dump()
[all …]
A Dintel_audio.c406 if (!HAS_DP20(display)) in intel_audio_sdp_split_update()
607 if (display->platform.valleyview || display->platform.cherryview) { in ibx_audio_regs_init()
899 else if (display->platform.valleyview || display->platform.cherryview || in intel_audio_hooks_init()
900 HAS_PCH_CPT(display) || HAS_PCH_IBX(display)) in intel_audio_hooks_init()
902 else if (display->platform.haswell || DISPLAY_VER(display) >= 8) in intel_audio_hooks_init()
1015 } else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) { in intel_audio_min_cdclk()
1035 if ((display->platform.valleyview || display->platform.cherryview) && in intel_audio_min_cdclk()
1120 if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display))) in intel_audio_component_get_cdclk_freq()
1185 if (!HAS_DDI(display)) in intel_audio_component_sync_audio_rate()
1298 drm_err(display->drm, in intel_audio_component_unbind()
[all …]
A Dintel_pps.c37 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
139 if (vlv_force_pll_on(display, pipe, vlv_get_dpll(display))) { in vlv_power_sequencer_kick()
356 if (display->platform.valleyview || display->platform.cherryview) in intel_num_pps()
359 if (display->platform.geminilake || display->platform.broxton) in intel_num_pps()
519 if (display->platform.geminilake || display->platform.broxton || in intel_pps_get_registers()
724 if (drm_WARN_ON(display->drm, !HAS_DDI(display) && in ilk_get_pp_control()
1638 } else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) { in pps_init_registers()
1776 if (!HAS_DISPLAY(display) || HAS_DDI(display)) in intel_pps_unlock_regs_wa()
1785 intel_de_rmw(display, PP_CONTROL(display, pps_idx), in intel_pps_unlock_regs_wa()
1791 if (HAS_PCH_SPLIT(display) || display->platform.geminilake || display->platform.broxton) in intel_pps_setup()
[all …]
A Dintel_vrr.c299 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), in intel_vrr_set_fixed_rr_timings()
301 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), in intel_vrr_set_fixed_rr_timings()
470 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
493 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
606 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), in intel_vrr_enable()
608 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), in intel_vrr_enable()
613 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_enable()
639 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_disable()
662 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_transcoder_enable()
667 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_transcoder_enable()
[all …]
/drivers/gpu/drm/xe/display/
A Dxe_display.c42 struct intel_display *display = xe->display; in has_display() local
94 struct intel_display *display = xe->display; in xe_display_fini_early() local
107 struct intel_display *display = xe->display; in xe_display_init_early() local
153 struct intel_display *display = xe->display; in xe_display_fini() local
163 struct intel_display *display = xe->display; in xe_display_init() local
178 struct intel_display *display = xe->display; in xe_display_register() local
189 struct intel_display *display = xe->display; in xe_display_unregister() local
202 struct intel_display *display = xe->display; in xe_display_irq_handler() local
213 struct intel_display *display = xe->display; in xe_display_irq_enable() local
224 struct intel_display *display = xe->display; in xe_display_irq_reset() local
[all …]
/drivers/gpu/drm/i915/
A DMakefile220 display/hsw_ips.o \
223 display/i9xx_wm.o \
228 display/intel_bo.o \
229 display/intel_bw.o \
261 display/intel_fb.o \
294 display/intel_tc.o \
297 display/intel_wm.o \
317 display/dvo_ivch.o \
321 display/g4x_dp.o \
323 display/icl_dsi.o \
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