Home
last modified time | relevance | path

Searched refs:display_config (Results 1 – 25 of 33) sorted by relevance

12

/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/
A Ddml2_pmo_dcn4_fams2.c952 for (i = 0; i < display_config->display_config.num_streams; i++) { in build_synchronized_timing_groups()
978 &display_config->display_config.stream_descriptors[j].timing, in build_synchronized_timing_groups()
997 for (i = 0; i < display_config->display_config.num_streams; i++) { in all_timings_support_vactive()
1016 for (i = 0; i < display_config->display_config.num_streams; i++) { in all_timings_support_vblank()
1091 for (i = 0; i < display_config->display_config.num_planes; i++) { in all_timings_support_svp()
1677 (display_config->display_config.num_streams - 1); in build_fams2_meta_per_stream()
1725 if (display_config->display_config.num_streams == 1) { in build_fams2_meta_per_stream()
1797 if (display_config->display_config.num_streams <= 1) { in build_fams2_meta_per_stream()
1855 if (display_config->display_config.overrides.all_streams_blanked) { in pmo_dcn4_fams2_init_for_pstate_support()
1896 display_config->display_config.num_streams, in pmo_dcn4_fams2_init_for_pstate_support()
[all …]
A Ddml2_pmo_dcn3.c205 for (i = 0; i < display_config->display_config.num_streams; i++) { in are_timings_trivially_synchronizable()
216 if (memcmp(&display_config->display_config.stream_descriptors[remap_array[i - 1]].timing, in are_timings_trivially_synchronizable()
217 &display_config->display_config.stream_descriptors[remap_array[i]].timing, in are_timings_trivially_synchronizable()
225 if (display_config->display_config.stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable()
282 const struct dml2_display_cfg *display_config = in pmo_dcn3_init_for_vmin() local
283 &in_out->base_display_config->display_config; in pmo_dcn3_init_for_vmin()
291 for (i = 0; i < display_config->num_planes; i++) in pmo_dcn3_init_for_vmin()
308 for (i = 0; i < display_config->num_streams; i++) { in pmo_dcn3_init_for_vmin()
343 const struct dml2_display_cfg *display_config, in find_highest_odm_load_stream_index() argument
368 const struct dml2_display_cfg *display_config = in pmo_dcn3_optimize_for_vmin() local
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml2_top_soc15.c14 memcpy(&out->display_config, display_config, sizeof(struct dml2_display_cfg)); in setup_unoptimized_display_config_with_meta()
20 memcpy(&out->display_config, display_config, sizeof(struct dml2_display_cfg)); in setup_speculative_display_config_with_meta()
67 l->test_mcache.calc_mcache_count_params.display_config = &params->display_config->display_config; in dml2_top_optimization_test_function_mcache()
74 …he.assign_global_mcache_ids_params.num_allocations = params->display_config->display_config.num_pl… in dml2_top_optimization_test_function_mcache()
79 …l->test_mcache.validate_admissibility_params.display_cfg = &params->display_config->display_config; in dml2_top_optimization_test_function_mcache()
103 l->optimize_mcache.optimize_mcache_params.display_config = &params->display_config->display_config; in dml2_top_optimization_optimize_function_mcache()
126 l->test_vmin.pmo_test_vmin_params.display_config = params->display_config; in dml2_top_optimization_test_function_vmin()
218 !params->display_config || in dml2_top_optimization_perform_optimization_phase()
290 !params->display_config || in dml2_top_optimization_perform_optimization_phase_1()
797 .display_config = &l->base_display_config_with_meta, in dml2_top_soc15_check_mode_supported()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4.c197 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in expand_implict_subvp()
202 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in expand_implict_subvp()
211 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in expand_implict_subvp()
212 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in expand_implict_subvp()
231 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in expand_implict_subvp()
232 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in expand_implict_subvp()
235 main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; in expand_implict_subvp()
266 …memcpy(&programming->display_config, &display_cfg->display_config, sizeof(struct dml2_display_cfg)… in pack_mode_programming_params_with_implicit_subvp()
282 for (stream_index = 0; stream_index < programming->display_config.num_streams; stream_index++) { in pack_mode_programming_params_with_implicit_subvp()
310 for (plane_index = 0; plane_index < programming->display_config.num_planes; plane_index++) { in pack_mode_programming_params_with_implicit_subvp()
[all …]
A Ddml2_core_utils.c616 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in dml2_core_utils_expand_implict_subvp()
621 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in dml2_core_utils_expand_implict_subvp()
630 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in dml2_core_utils_expand_implict_subvp()
631 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in dml2_core_utils_expand_implict_subvp()
650 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in dml2_core_utils_expand_implict_subvp()
651 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in dml2_core_utils_expand_implict_subvp()
654 main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; in dml2_core_utils_expand_implict_subvp()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_wrapper.c28 (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; in dml21_allocate_memory()
29 (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; in dml21_allocate_memory()
111 dml_phantom_prog_idx = in_ctx->v21.mode_programming.programming->display_config.num_planes; in dml21_calculate_rq_and_dlg_params()
210 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); in dml21_mode_check_and_programming()
270 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); in dml21_check_mode_support()
326 dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; in dml21_prepare_mcache_programming()
329 …for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.nu… in dml21_prepare_mcache_programming()
380 …for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.nu… in dml21_prepare_mcache_programming()
437 dst_dml_ctx->v21.mode_support.display_config = &dst_dml_ctx->v21.display_config; in dml21_copy()
438 dst_dml_ctx->v21.mode_programming.display_config = dst_dml_ctx->v21.mode_support.display_config; in dml21_copy()
A Ddml21_utils.c330 …x = 0; dml_stream_index < dml_ctx->v21.mode_programming.programming->display_config.num_streams; d… in dml21_handle_phantom_streams_planes()
353 …ex = 0; dml_plane_index < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dm… in dml21_handle_phantom_streams_planes()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dhardwaremanager.c295 const struct amd_pp_display_configuration *display_config) in phm_store_dal_configuration_data() argument
302 if (display_config == NULL) in phm_store_dal_configuration_data()
306 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk); in phm_store_dal_configuration_data()
308 for (index = 0; index < display_config->num_path_including_non_display; index++) { in phm_store_dal_configuration_data()
309 if (display_config->displays[index].controller_id != 0) in phm_store_dal_configuration_data()
323 display_config->cpu_pstate_separation_time, in phm_store_dal_configuration_data()
324 display_config->cpu_cc6_disable, in phm_store_dal_configuration_data()
325 display_config->cpu_pstate_disable, in phm_store_dal_configuration_data()
326 display_config->nb_pstate_switch_disable); in phm_store_dal_configuration_data()
A Dvega12_hwmgr.c1623 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()
1624 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()
1625 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()
1630 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1631 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1632 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
2366 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()
2367 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()
2369 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()
2436 if (hwmgr->display_config->nb_pstate_switch_disable) in vega12_apply_clocks_adjust_rules()
[all …]
A Dvega20_hwmgr.c2358 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2359 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2360 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
3673 hwmgr->display_config->num_display, in vega20_display_configuration_changed_task()
3748 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_apply_clocks_adjust_rules()
3749 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_apply_clocks_adjust_rules()
3751 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules()
3818 if (hwmgr->display_config->nb_pstate_switch_disable) in vega20_apply_clocks_adjust_rules()
3834 if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching) in vega20_apply_clocks_adjust_rules()
3923 hwmgr->display_config->num_display) in vega20_check_smc_update_required_for_display_configuration()
[all …]
A Dsmu10_hwmgr.c194 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_set_clock_limit()
628 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_dpm_force_dpm_level()
629 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
785 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
A Dsmu7_hwmgr.c3356 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
3357 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()
3387 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules()
3388 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules()
3389 (hwmgr->display_config->num_display && in smu7_apply_state_adjust_rules()
3390 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); in smu7_apply_state_adjust_rules()
3395 if (hwmgr->display_config->num_display == 0) { in smu7_apply_state_adjust_rules()
3437 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in smu7_apply_state_adjust_rules()
4592 refresh_rate = hwmgr->display_config->vrefresh; in smu7_program_display_gap()
4689 if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh) in smu7_check_smc_update_required_for_display_configuration()
[all …]
A Dvega10_hwmgr.c3328 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3329 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()
3369 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()
3372 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules()
3373 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules()
4110 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()
4111 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()
4112 !hwmgr->display_config->nb_pstate_switch_disable) in vega10_notify_smc_display_config_after_ps_adjustment()
4117 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()
4119 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
[all …]
A Dsmu8_hwmgr.c711 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()
769 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()
1093 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()
1094 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()
1102 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
A Ddml2_internal_shared_types.h342 struct dml2_display_cfg display_config; member
512 const struct dml2_display_cfg *display_config; member
535 const struct display_configuation_with_meta *display_config; member
780 const struct dml2_display_cfg *display_config; member
875 struct display_configuation_with_meta *display_config; member
881 struct display_configuation_with_meta *display_config; member
888 struct display_configuation_with_meta *display_config; member
894 const struct display_configuation_with_meta *display_config; // Initial Display Configuration member
949 const struct dml2_display_cfg *display_config; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c60 if (in_out->display_cfg->display_config.hostvm_enable) in calculate_system_active_minimums()
397 for (i = 0; i < display_cfg->display_config.num_streams; i++) { in map_min_clocks_to_dpm()
415 static bool are_timings_trivially_synchronizable(struct dml2_display_cfg *display_config, int mask) in are_timings_trivially_synchronizable() argument
424 for (i = 0; i < display_config->num_streams; i++) { in are_timings_trivially_synchronizable()
436 …if (memcmp(&display_config->stream_descriptors[remap_array[i - 1]].timing, &display_config->stream… in are_timings_trivially_synchronizable()
444 if (display_config->stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable()
463 for (i = 0; i < in_out->programming->display_config.num_streams; i++) { in find_smallest_idle_time_in_vblank_us()
486 if (are_timings_trivially_synchronizable(&in_out->programming->display_config, 0xF)) { in determine_power_management_features_with_vblank_only()
505 for (i = 0; i < in_out->programming->display_config.num_planes; i++) { in get_displays_without_vactive_margin_mask()
519 for (i = 0; i < in_out->programming->display_config.num_planes; i++) { in get_displays_with_fams_mask()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_types.h101 const struct dml2_display_cfg *display_config; member
363 struct dml2_display_cfg display_config; member
699 const struct dml2_display_cfg *display_config; member
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_internal_types.h149 struct dml2_display_cfg display_config; member
/drivers/gpu/drm/amd/pm/powerplay/inc/
A Dhardwaremanager.h427 const struct amd_pp_display_configuration *display_config);
/drivers/gpu/drm/amd/pm/powerplay/
A Damd_powerplay.c63 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
1027 const struct amd_pp_display_configuration *display_config) in pp_display_configuration_change() argument
1034 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dvegam_smumgr.c839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in vegam_populate_single_graphic_level()
843 hwmgr->display_config->min_core_set_clock_in_sr); in vegam_populate_single_graphic_level()
1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in vegam_populate_single_memory_level()
1014 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in vegam_populate_single_memory_level()
A Dfiji_smumgr.c974 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in fiji_populate_single_graphic_level()
978 hwmgr->display_config->min_core_set_clock_in_sr); in fiji_populate_single_graphic_level()
1199 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in fiji_populate_single_memory_level()
1200 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in fiji_populate_single_memory_level()
A Dpolaris10_smumgr.c993 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in polaris10_populate_single_graphic_level()
997 hwmgr->display_config->min_core_set_clock_in_sr); in polaris10_populate_single_graphic_level()
1188 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in polaris10_populate_single_memory_level()
1189 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in polaris10_populate_single_memory_level()
/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c1342 smu->display_config = &adev->pm.pm_display_cfg; in smu_sw_init()
2251 const struct amd_pp_display_configuration *display_config) in smu_display_configuration_change() argument
2258 if (!display_config) in smu_display_configuration_change()
2262 display_config->min_dcef_deep_sleep_set_clk / 100); in smu_display_configuration_change()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsienna_cichlid_ppt.c1566 smu->display_config->num_display, in sienna_cichlid_display_config_changed()
1837 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in sienna_cichlid_notify_smc_display_config()
1838 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in sienna_cichlid_notify_smc_display_config()
1839 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()

Completed in 154 milliseconds

12