Searched refs:display_v_end (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/msm/disp/mdp4/ |
| A D | mdp4_dsi_encoder.c | 35 uint32_t display_v_start, display_v_end; in mdp4_dsi_encoder_mode_set() local
57 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dsi_hsync_s… in mdp4_dsi_encoder_mode_set()
68 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end); in mdp4_dsi_encoder_mode_set()
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| A D | mdp4_dtv_encoder.c | 35 uint32_t display_v_start, display_v_end; in mdp4_dtv_encoder_mode_set() local
61 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp4_dtv_encoder_mode_set()
72 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); in mdp4_dtv_encoder_mode_set()
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| A D | mdp4_lcdc_encoder.c | 208 uint32_t display_v_start, display_v_end; in mdp4_lcdc_encoder_mode_set() local
234 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_… in mdp4_lcdc_encoder_mode_set()
245 mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VEND, display_v_end); in mdp4_lcdc_encoder_mode_set()
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| /drivers/gpu/drm/msm/disp/mdp5/ |
| A D | mdp5_encoder.c | 29 uint32_t display_v_start, display_v_end; in mdp5_vid_encoder_mode_set() local
79 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp5_vid_encoder_mode_set()
88 display_v_end -= mode->hsync_start - mode->hdisplay; in mdp5_vid_encoder_mode_set()
102 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end); in mdp5_vid_encoder_mode_set()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_hw_intf.c | 105 u32 display_v_start, display_v_end; in dpu_hw_intf_setup_timing_engine() local
131 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + in dpu_hw_intf_setup_timing_engine()
193 display_v_end -= p->h_front_porch; in dpu_hw_intf_setup_timing_engine()
229 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); in dpu_hw_intf_setup_timing_engine()
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| /drivers/gpu/drm/msm/dp/ |
| A D | dp_panel.c | 302 u32 display_v_start, display_v_end; in msm_dp_panel_tpg_enable() local
314 display_v_end = ((vsync_period - (drm_mode->vsync_start - in msm_dp_panel_tpg_enable()
319 display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay); in msm_dp_panel_tpg_enable()
342 msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); in msm_dp_panel_tpg_enable()
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