| /drivers/gpu/drm/nouveau/dispnv50/ |
| A D | head.c | 73 if (asyh->set.dither ) head->func->dither (head, asyh); in nv50_head_flush_set()
99 if (asyc->dither.mode) { in nv50_head_atomic_check_dither()
100 if (asyc->dither.mode == DITHERING_MODE_AUTO) { in nv50_head_atomic_check_dither()
104 mode = asyc->dither.mode; in nv50_head_atomic_check_dither()
107 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) { in nv50_head_atomic_check_dither()
111 mode |= asyc->dither.depth; in nv50_head_atomic_check_dither()
116 asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS); in nv50_head_atomic_check_dither()
118 asyh->set.dither = true; in nv50_head_atomic_check_dither()
366 asyc->set.dither = true; in nv50_head_atomic_check()
384 if (asyc->set.dither) in nv50_head_atomic_check()
[all …]
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| A D | head917d.c | 41 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in head917d_dither()
42 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in head917d_dither()
43 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head917d_dither()
135 .dither = head917d_dither,
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| A D | headca7d.c | 101 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in headca7d_dither()
102 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in headca7d_dither()
104 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in headca7d_dither()
292 .dither = headca7d_dither,
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| A D | headc37d.c | 96 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in headc37d_dither()
97 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in headc37d_dither()
99 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in headc37d_dither()
296 .dither = headc37d_dither,
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| A D | atom.h | 108 } dither; member
142 bool dither:1; member
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| A D | head507d.c | 59 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in head507d_dither()
60 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in head507d_dither()
61 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head507d_dither()
447 .dither = head507d_dither,
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| A D | head907d.c | 88 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in head907d_dither()
89 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in head907d_dither()
90 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head907d_dither()
430 .dither = head907d_dither,
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| A D | head.h | 50 int (*dither)(struct nv50_head *, struct nv50_head_atom *); member
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| A D | head827d.c | 166 .dither = head507d_dither,
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| A D | headc57d.c | 261 .dither = headc37d_dither,
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| /drivers/gpu/drm/nouveau/ |
| A D | nouveau_connector.c | 114 *val = asyc->dither.mode; in nouveau_conn_atomic_get_property()
116 *val = asyc->dither.depth; in nouveau_conn_atomic_get_property()
192 if (asyc->dither.mode != val) { in nouveau_conn_atomic_set_property()
193 asyc->dither.mode = val; in nouveau_conn_atomic_set_property()
194 asyc->set.dither = true; in nouveau_conn_atomic_set_property()
198 if (asyc->dither.mode != val) { in nouveau_conn_atomic_set_property()
199 asyc->dither.depth = val; in nouveau_conn_atomic_set_property()
200 asyc->set.dither = true; in nouveau_conn_atomic_set_property()
238 asyc->dither = armc->dither; in nouveau_conn_atomic_duplicate_state()
350 armc->dither.mode); in nouveau_conn_attach_properties()
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| A D | nouveau_connector.h | 89 } dither; member
112 bool dither:1; member
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| /drivers/gpu/drm/i915/display/ |
| A D | dvo_ns2501.c | 209 u8 dither; /* configuration of the dithering */ member
236 .dither = 0x0f,
256 .dither = 0x0f,
275 .dither = 0x0f,
639 ns2501_writeb(dvo, NS2501_REGF9, conf->dither); in ns2501_mode_set()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| A D | dfp.c | 422 regp->dither = savep->dither | 0x00010000; in nv04_dfp_mode_set()
425 regp->dither = savep->dither | 0x00000001; in nv04_dfp_mode_set()
440 regp->dither = savep->dither; in nv04_dfp_mode_set()
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| A D | hw.c | 408 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); in nv_save_state_ramdac()
433 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); in nv_save_state_ramdac()
485 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); in nv_load_state_ramdac()
511 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); in nv_load_state_ramdac()
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| A D | disp.h | 58 uint32_t dither; member
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| /drivers/gpu/drm/radeon/ |
| A D | rs600.c | 172 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; in avivo_program_fmt() local
177 dither = radeon_connector->dither; in avivo_program_fmt()
189 if (dither == RADEON_FMT_DITHER_ENABLE) in avivo_program_fmt()
196 if (dither == RADEON_FMT_DITHER_ENABLE) in avivo_program_fmt()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_hw_catalog.c | 411 .dither = {.name = "dither", .base = 0x30e0,
416 .dither = {.name = "dither", .base = 0xe0,
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| A D | dpu_kms.c | 987 if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0) in dpu_kms_mdp_snapshot()
988 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len, in dpu_kms_mdp_snapshot()
989 base + cat->pingpong[i].sblk->dither.base, in dpu_kms_mdp_snapshot()
991 cat->pingpong[i].sblk->dither.name); in dpu_kms_mdp_snapshot()
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| A D | dpu_hw_pingpong.c | 54 base = pp->caps->sblk->dither.base; in dpu_hw_pp_setup_dither()
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| A D | dpu_hw_catalog.h | 324 struct dpu_pp_blk dither; member
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| /drivers/video/fbdev/nvidia/ |
| A D | nv_type.h | 62 u32 dither; member
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| A D | nvidia.c | 472 state->dither = NV_RD32(par->PRAMDAC, 0x0528) & in nvidia_calc_regs()
475 state->dither |= 0x00010000; in nvidia_calc_regs()
477 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; in nvidia_calc_regs()
479 state->dither |= 1; in nvidia_calc_regs()
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| /drivers/ps3/ |
| A D | ps3av_cmd.c | 356 av_video_cs->dither = PS3AV_CMD_AV_DITHER_ON in ps3av_cmd_set_av_video_cs()
360 av_video_cs->dither = PS3AV_CMD_AV_DITHER_OFF; in ps3av_cmd_set_av_video_cs()
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| /drivers/media/platform/mediatek/mdp3/ |
| A D | mtk-mdp3-regs.h | 319 u32 dither:1; member
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