| /drivers/clk/baikal-t1/ |
| A D | ccu-div.c | 92 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
102 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
123 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_enable()
268 regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, val); in ccu_div_var_set_rate_slow()
359 struct ccu_div *div = bit->div; in ccu_div_dbgfs_bit_set() local
381 regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, data); in ccu_div_dbgfs_var_clkdiv_set()
400 struct ccu_div *div = bit->div; in ccu_div_dbgfs_bit_get() local
465 bits[didx].div = div; in ccu_div_var_debug_init()
492 bit->div = div; in ccu_div_gate_debug_init()
510 bit->div = div; in ccu_div_buf_debug_init()
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| /drivers/clk/berlin/ |
| A D | berlin2-div.c | 71 if (div->lock) in berlin2_div_is_enabled()
77 if (div->lock) in berlin2_div_is_enabled()
89 if (div->lock) in berlin2_div_enable()
96 if (div->lock) in berlin2_div_enable()
108 if (div->lock) in berlin2_div_disable()
115 if (div->lock) in berlin2_div_disable()
125 if (div->lock) in berlin2_div_set_parent()
144 if (div->lock) in berlin2_div_set_parent()
239 div = kzalloc(sizeof(*div), GFP_KERNEL); in berlin2_div_register()
240 if (!div) in berlin2_div_register()
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| /drivers/clk/ti/ |
| A D | divider.c | 77 if (clkt->div == div) in _get_table_val()
85 return div; in _get_val()
103 if (!div) { in ti_clk_divider_recalc_rate()
125 if (clkt->div == div) in _is_valid_table_div()
147 if (clkt->div == div) in _div_round_up()
149 else if (clkt->div < div) in _div_round_up()
152 if ((clkt->div - div) < (up - div)) in _div_round_up()
229 int div; in ti_clk_divider_round_rate() local
480 div->shift = div->reg.bit; in ti_clk_divider_populate()
518 div = kzalloc(sizeof(*div), GFP_KERNEL); in of_ti_divider_clk_setup()
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| /drivers/clk/imx/ |
| A D | clk-divider-gate.c | 32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
54 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate()
64 div->flags, div->width); in clk_divider_gate_recalc_rate()
83 div->width, div->flags); in clk_divider_gate_set_rate()
91 val &= ~(clk_div_mask(div->width) << div->shift); in clk_divider_gate_set_rate()
117 val = readl(div->reg); in clk_divider_enable()
119 writel(val, div->reg); in clk_divider_enable()
136 val = readl(div->reg) >> div->shift; in clk_divider_disable()
139 writel(0, div->reg); in clk_divider_disable()
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| /drivers/clk/ |
| A D | clk-divider.c | 115 if (clkt->div == div) in _get_table_val()
174 if (clkt->div == div) in _is_valid_table_div()
195 if (clkt->div == div) in _round_up_table()
197 else if (clkt->div < div) in _round_up_table()
200 if ((clkt->div - div) < (up - div)) in _round_up_table()
213 if (clkt->div == div) in _round_down_table()
215 else if (clkt->div > div) in _round_down_table()
218 if ((div - clkt->div) < (div - down)) in _round_down_table()
232 div = __roundup_pow_of_two(div); in _div_round_up()
234 div = _round_up_table(table, div); in _div_round_up()
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| A D | clk-fsl-flexspi.c | 14 { .val = 0, .div = 1, },
15 { .val = 1, .div = 2, },
16 { .val = 2, .div = 3, },
17 { .val = 3, .div = 4, },
18 { .val = 4, .div = 5, },
19 { .val = 5, .div = 6, },
20 { .val = 6, .div = 7, },
21 { .val = 7, .div = 8, },
33 { .val = 1, .div = 2, },
34 { .val = 3, .div = 4, },
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| A D | clk-milbeaut.c | 83 u8 div; member
105 { .div = 0 },
111 { .div = 0 },
117 { .div = 0 },
123 { .div = 0 },
129 { .div = 0 },
135 { .div = 0 },
143 { .div = 0 },
149 { .div = 0 },
468 div = kzalloc(sizeof(*div), GFP_KERNEL); in m10v_clk_hw_register_divider()
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| A D | clk-cdce706.c | 29 #define CDCE706_DIVIDER(div) (13 + (div)) argument
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
51 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
72 unsigned div; member
180 if (hwd->div) in cdce706_pll_recalc_rate()
201 hwd->div = div; in cdce706_pll_round_rate()
216 unsigned long mul = hwd->mul, div = hwd->div; in cdce706_pll_set_rate() local
286 if (hwd->div) in cdce706_divider_recalc_rate()
316 div <= CDCE706_PLL_FREQ_MAX / rate; ++div) { in cdce706_divider_determine_rate()
351 hwd->div = div; in cdce706_divider_determine_rate()
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| A D | clk-fixed-factor.c | 29 do_div(rate, fix->div); in clk_factor_recalc_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
117 fix->div = div; in __clk_hw_register_fixed_factor()
165 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_index() argument
211 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor() argument
239 &pdata, flags, mult, div, acc, in clk_hw_register_fixed_factor_with_accuracy_fwname()
246 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor_index() argument
257 unsigned int mult, unsigned int div) in clk_register_fixed_factor() argument
262 div); in clk_register_fixed_factor()
323 &pdata, flags, mult, div, acc, in devm_clk_hw_register_fixed_factor_with_accuracy_fwname()
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| /drivers/clk/sophgo/ |
| A D | clk-cv18xx-ip.c | 137 if (!div || div->initval < 0 || (div->width == 0 && div->initval <= 0)) in div_helper_get_clockdiv()
264 val = div_helper_get_clockdiv(&div->common, &div->div); in div_recalc_rate()
269 div->div.flags, div->div.width); in div_recalc_rate()
279 div->div.width, div->div.flags); in div_set_rate()
313 -1, &div->div); in bypass_div_round_rate()
336 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_recalc_rate()
347 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_set_rate()
683 div = &mmux->div[0]; in mmux_recalc_rate()
685 div = &mmux->div[1]; in mmux_recalc_rate()
706 div = &mmux->div[0]; in mmux_set_rate()
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| /drivers/clk/sunxi/ |
| A D | clk-sunxi.c | 35 u8 div; in sun4i_get_pll1_factors() local
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
61 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
159 u8 div; in sun8i_a23_get_pll1_factors() local
176 if (div < 20 || (div < 32 && (div & 1))) in sun8i_a23_get_pll1_factors()
181 else if (div < 40 || (div < 64 && (div & 2))) in sun8i_a23_get_pll1_factors()
203 u8 div; in sun4i_get_pll5_factors() local
230 u8 div; in sun6i_a31_get_pll6_factors() local
251 u32 div; in sun5i_a13_get_ahb_factors() local
348 int div; in sun4i_get_apb1_factors() local
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| A D | clk-sun9i-cpus.c | 72 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
86 if (div < 32) { in sun9i_a80_cpus_clk_round()
87 pre_div = div; in sun9i_a80_cpus_clk_round()
88 div = 1; in sun9i_a80_cpus_clk_round()
89 } else if (div < 64) { in sun9i_a80_cpus_clk_round()
91 div = 2; in sun9i_a80_cpus_clk_round()
92 } else if (div < 96) { in sun9i_a80_cpus_clk_round()
94 div = 3; in sun9i_a80_cpus_clk_round()
97 div = 4; in sun9i_a80_cpus_clk_round()
103 *divp = div - 1; in sun9i_a80_cpus_clk_round()
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| /drivers/clk/mxs/ |
| A D | clk-div.c | 40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
59 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div() local
77 div = kzalloc(sizeof(*div), GFP_KERNEL); in mxs_clk_div()
78 if (!div) in mxs_clk_div()
87 div->reg = reg; in mxs_clk_div()
88 div->busy = busy; in mxs_clk_div()
90 div->divider.reg = reg; in mxs_clk_div()
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| /drivers/clk/bcm/ |
| A D | clk-iproc-asiu.c | 22 struct iproc_asiu_div div; member
89 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
91 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
104 unsigned int div; in iproc_asiu_clk_round_rate() local
113 if (div < 2) in iproc_asiu_clk_round_rate()
116 return *parent_rate / div; in iproc_asiu_clk_round_rate()
139 if (div < 2) in iproc_asiu_clk_set_rate()
142 div_h = div_l = div >> 1; in iproc_asiu_clk_set_rate()
157 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); in iproc_asiu_clk_set_rate()
160 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); in iproc_asiu_clk_set_rate()
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| A D | clk-kona.c | 60 if (divider_is_fixed(div)) in scaled_div_min()
61 return (u64)div->u.fixed; in scaled_div_min()
71 if (divider_is_fixed(div)) in scaled_div_max()
553 reg_div = bitfield_extract(reg_val, div->u.s.shift, div->u.s.width); in divider_read_scaled()
584 div->u.s.width); in __div_commit()
585 div->u.s.scaled_div = scaled_div_value(div, reg_div); in __div_commit()
591 reg_div = divider(div, div->u.s.scaled_div); in __div_commit()
602 reg_val = bitfield_replace(reg_val, div->u.s.shift, div->u.s.width, in __div_commit()
625 if (!divider_exists(div) || divider_is_fixed(div)) in div_init()
987 struct bcm_clk_div *div = &bcm_clk->u.peri->div; in kona_peri_clk_round_rate() local
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| /drivers/clk/ingenic/ |
| A D | cgu.c | 420 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
424 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
426 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
445 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
480 div = clamp_t(unsigned int, div, clk_info->div.div, in ingenic_clk_calc_div()
481 clk_info->div.div << clk_info->div.bits); in ingenic_clk_calc_div()
488 div = DIV_ROUND_UP(div, clk_info->div.div); in ingenic_clk_calc_div()
489 div *= clk_info->div.div; in ingenic_clk_calc_div()
491 return div; in ingenic_clk_calc_div()
505 div = clk_info->fixdiv.div; in ingenic_clk_determine_rate()
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| /drivers/mmc/host/ |
| A D | meson-mx-sdhc-clkc.c | 17 struct clk_divider div; member
32 { .div = 6, .val = 5, },
33 { .div = 8, .val = 7, },
34 { .div = 9, .val = 8, },
35 { .div = 10, .val = 9, },
36 { .div = 12, .val = 11, },
37 { .div = 16, .val = 15, },
38 { .div = 18, .val = 17, },
39 { .div = 34, .val = 33, },
115 clkc_data->div.shift = 0; in meson_mx_sdhc_register_clkc()
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| /drivers/clk/meson/ |
| A D | clk-regmap.c | 117 val >>= div->shift; in clk_regmap_div_recalc_rate()
118 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()
119 return divider_recalc_rate(hw, prate, val, div->table, div->flags, in clk_regmap_div_recalc_rate()
120 div->width); in clk_regmap_div_recalc_rate()
137 val >>= div->shift; in clk_regmap_div_determine_rate()
141 div->width, div->flags, val); in clk_regmap_div_determine_rate()
144 return divider_determine_rate(hw, req, div->table, div->width, in clk_regmap_div_determine_rate()
145 div->flags); in clk_regmap_div_determine_rate()
156 ret = divider_get_val(rate, parent_rate, div->table, div->width, in clk_regmap_div_set_rate()
157 div->flags); in clk_regmap_div_set_rate()
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| /drivers/clk/spear/ |
| A D | spear1340_clock.c | 240 {.div = 0x08000},
241 {.div = 0x06a38},
242 {.div = 0x06666},
243 {.div = 0x06000},
244 {.div = 0x054FD},
245 {.div = 0x05000},
246 {.div = 0x04D18},
247 {.div = 0x04CCE},
248 {.div = 0x04000},
249 {.div = 0x039D5},
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| /drivers/clk/tegra/ |
| A D | clk-divider.c | 24 int div; in get_div() local
29 if (div < 0) in get_div()
32 return div; in get_div()
40 int div, mul; in clk_frac_div_recalc_rate() local
52 div += mul; in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_round_rate() local
72 if (div < 0) in clk_frac_div_round_rate()
84 int div; in clk_frac_div_set_rate() local
89 if (div < 0) in clk_frac_div_set_rate()
90 return div; in clk_frac_div_set_rate()
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| /drivers/clk/sprd/ |
| A D | div.c | 18 cd->div.width, 0); in sprd_div_round_rate()
22 const struct sprd_div_internal *div, in sprd_div_helper_recalc_rate() argument
29 val = reg >> div->shift; in sprd_div_helper_recalc_rate()
30 val &= (1 << div->width) - 1; in sprd_div_helper_recalc_rate()
33 div->width); in sprd_div_helper_recalc_rate()
46 const struct sprd_div_internal *div, in sprd_div_helper_set_rate() argument
54 div->width, 0); in sprd_div_helper_set_rate()
57 reg &= ~GENMASK(div->width + div->shift - 1, div->shift); in sprd_div_helper_set_rate()
59 regmap_write(common->regmap, common->reg + div->offset, in sprd_div_helper_set_rate()
60 reg | (val << div->shift)); in sprd_div_helper_set_rate()
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| /drivers/clk/x86/ |
| A D | clk-cgu.c | 168 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, in lgm_clk_divider_enable_disable()
207 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); in lgm_clk_register_divider()
208 if (!div) in lgm_clk_register_divider()
218 div->reg = reg; in lgm_clk_register_divider()
227 hw = &div->hw; in lgm_clk_register_divider()
471 div = DIV_ROUND_CLOSEST_ULL((u64)div, 5); in lgm_clk_ddiv_set_rate()
472 div = div * 2; in lgm_clk_ddiv_set_rate()
475 if (div <= 0) in lgm_clk_ddiv_set_rate()
502 div = div * 2; in lgm_clk_ddiv_round_rate()
503 div = DIV_ROUND_CLOSEST_ULL((u64)div, 5); in lgm_clk_ddiv_round_rate()
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| /drivers/media/platform/st/sti/hva/ |
| A D | hva-debugfs.c | 121 u64 div; in hva_dbg_perf_begin() local
132 do_div(div, 100); in hva_dbg_perf_begin()
133 period = (u32)div; in hva_dbg_perf_begin()
154 bitrate = (u32)div; in hva_dbg_perf_begin()
178 u64 div; in hva_dbg_perf_end() local
188 do_div(div, 1000); in hva_dbg_perf_end()
189 timestamp = (u32)div; in hva_dbg_perf_end()
199 bytesused, (u32)div); in hva_dbg_perf_end()
201 do_div(div, 100); in hva_dbg_perf_end()
202 duration = (u32)div; in hva_dbg_perf_end()
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| /drivers/clk/zynqmp/ |
| A D | divider.c | 86 u32 div, value; in zynqmp_clk_divider_recalc_rate() local
96 value = div & 0xFFFF; in zynqmp_clk_divider_recalc_rate()
98 value = div >> 16; in zynqmp_clk_divider_recalc_rate()
176 u32 value, div; in zynqmp_clk_divider_set_rate() local
184 div = 0xffff; in zynqmp_clk_divider_set_rate()
185 div |= value << 16; in zynqmp_clk_divider_set_rate()
189 div = __ffs(div); in zynqmp_clk_divider_set_rate()
284 div = kzalloc(sizeof(*div), GFP_KERNEL); in zynqmp_clk_register_divider()
285 if (!div) in zynqmp_clk_register_divider()
313 hw = &div->hw; in zynqmp_clk_register_divider()
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| /drivers/clk/at91/ |
| A D | clk-sam9x60-pll.c | 47 u8 div; member
378 sam9x60_div_pll_set_div(core, div->div, 1); in sam9x60_div_pll_set()
504 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; in sam9x60_div_pll_set_rate()
518 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; in sam9x60_div_pll_set_rate_chg()
527 if (cdiv == div->div) in sam9x60_div_pll_set_rate_chg()
530 sam9x60_div_pll_set_div(core, div->div, 0); in sam9x60_div_pll_set_rate_chg()
574 div->div = div->safe_div; in sam9x60_div_pll_notifier_fn()
586 sam9x60_div_pll_set_div(&core, div->div, 0); in sam9x60_div_pll_notifier_fn()
740 div = kzalloc(sizeof(*div), GFP_KERNEL); in sam9x60_clk_register_div_pll()
741 if (!div) in sam9x60_clk_register_div_pll()
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