Searched refs:div_factor (Results 1 – 8 of 8) sorted by relevance
| /drivers/clk/qcom/ |
| A D | clk-spmi-pmic-div.c | 41 if (!div_factor) in div_factor_to_div()
42 div_factor = 1; in div_factor_to_div()
44 return 1 << (div_factor - 1); in div_factor_to_div()
63 unsigned int div_factor) in __spmi_pmic_clkdiv_set_enable_state() argument
84 unsigned int div_factor; in spmi_pmic_clkdiv_set_enable_state() local
87 div_factor &= DIV_CTL1_DIV_FACTOR_MASK; in spmi_pmic_clkdiv_set_enable_state()
118 unsigned int div, div_factor; in clk_spmi_pmic_div_determine_rate() local
121 div_factor = div_to_div_factor(div); in clk_spmi_pmic_div_determine_rate()
122 div = div_factor_to_div(div_factor); in clk_spmi_pmic_div_determine_rate()
133 unsigned int div_factor; in clk_spmi_pmic_div_recalc_rate() local
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| /drivers/media/dvb-frontends/ |
| A D | ix2505v.c | 124 u32 div_factor, N , A, x; in ix2505v_set_params() local
147 div_factor = (frequency * ref) / 40; /* local osc = 4Mhz */ in ix2505v_set_params()
148 x = div_factor / psc; in ix2505v_set_params()
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| /drivers/media/platform/qcom/iris/ |
| A D | iris_buffer.c | 202 u32 div_factor = 2; in iris_bitstream_buffer_size() local
206 div_factor = 4; in iris_bitstream_buffer_size()
210 div_factor = 1; in iris_bitstream_buffer_size()
217 frame_size = base_res_mbs * (16 * 16) * 3 / 2 / div_factor; in iris_bitstream_buffer_size()
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| /drivers/media/platform/qcom/venus/ |
| A D | hfi_plat_bufs_v6.c | 1122 u32 div_factor = 1; in calculate_dec_input_frame_size() local
1134 div_factor = 4; in calculate_dec_input_frame_size()
1139 div_factor = 1; in calculate_dec_input_frame_size()
1141 div_factor = 2; in calculate_dec_input_frame_size()
1144 frame_size = base_res_mbs * MB_SIZE_IN_PIXEL * 3 / 2 / div_factor; in calculate_dec_input_frame_size()
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| /drivers/platform/x86/intel/speed_select_if/ |
| A D | isst_tpmi_core.c | 577 #define _write_cp_info(name_str, name, offset, start, width, div_factor)\ argument
585 val |= (name / div_factor) << start;\
792 #define _write_pp_info(name_str, name, offset, start, width, div_factor)\ argument
800 val |= (name / div_factor) << start;\
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_clock_source.c | 990 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); in dcn31_program_pix_clk()
1095 dto_params.refclk_hz *= e->div_factor; in dcn401_program_pix_clk()
1344 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); in dcn3_program_pix_clk()
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| A D | dce_clock_source.h | 324 unsigned short div_factor; member
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| /drivers/dpll/zl3073x/ |
| A D | dpll.c | 578 s64 conn_period, div_factor; in zl3073x_dpll_input_pin_phase_offset_get() local
581 div_factor = div64_s64(ref_phase, conn_period); in zl3073x_dpll_input_pin_phase_offset_get()
582 ref_phase -= conn_period * div_factor; in zl3073x_dpll_input_pin_phase_offset_get()
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