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Searched refs:div_l (Results 1 – 5 of 5) sorted by relevance

/drivers/clk/bcm/
A Dclk-iproc-asiu.c74 unsigned int div_h, div_l; in iproc_asiu_clk_recalc_rate() local
91 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
92 div_l++; in iproc_asiu_clk_recalc_rate()
94 clk->rate = parent_rate / (div_h + div_l); in iproc_asiu_clk_recalc_rate()
96 __func__, clk->rate, parent_rate, div_h, div_l); in iproc_asiu_clk_recalc_rate()
124 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
142 div_h = div_l = div >> 1; in iproc_asiu_clk_set_rate()
144 div_l--; in iproc_asiu_clk_set_rate()
156 if (div_l) { in iproc_asiu_clk_set_rate()
158 val |= div_l << clk->div.low_shift; in iproc_asiu_clk_set_rate()
/drivers/hwmon/
A Daspeed-g6-pwm-tach.c156 u64 div_h, div_l, duty_cycle_period, dividend; in aspeed_pwm_get_state() local
163 div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val); in aspeed_pwm_get_state()
176 dividend = (u64)NSEC_PER_SEC * (div_l + 1) * duty_pt in aspeed_pwm_get_state()
192 u64 div_h, div_l, divisor, expect_period; in aspeed_pwm_apply() local
212 if (div_l == 0) in aspeed_pwm_apply()
215 div_l -= 1; in aspeed_pwm_apply()
217 if (div_l > 255) in aspeed_pwm_apply()
218 div_l = 255; in aspeed_pwm_apply()
221 priv->clk_rate, div_h, div_l); in aspeed_pwm_apply()
224 (u64)NSEC_PER_SEC * (div_l + 1) << div_h); in aspeed_pwm_apply()
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A Daspeed-pwm-tacho.c508 u8 clk_unit, div_h, div_l, tacho_div; in aspeed_get_fan_tach_ch_measure_period() local
514 div_l = priv->type_pwm_clock_division_l[type]; in aspeed_get_fan_tach_ch_measure_period()
515 if (div_l == 0) in aspeed_get_fan_tach_ch_measure_period()
516 div_l = 1; in aspeed_get_fan_tach_ch_measure_period()
518 div_l = div_l * 2; in aspeed_get_fan_tach_ch_measure_period()
524 return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit); in aspeed_get_fan_tach_ch_measure_period()
/drivers/i2c/busses/
A Di2c-meson.c142 unsigned int div_h, div_l; in meson_gxbb_axg_i2c_set_clk_div() local
153 div_l = DIV_ROUND_UP(div_h, 4); in meson_gxbb_axg_i2c_set_clk_div()
157 div_l = DIV_ROUND_UP(clk_rate * 3, freq * 5 * 2); in meson_gxbb_axg_i2c_set_clk_div()
165 if (div_l > GENMASK(11, 0)) { in meson_gxbb_axg_i2c_set_clk_div()
167 div_l = GENMASK(11, 0); in meson_gxbb_axg_i2c_set_clk_div()
178 FIELD_PREP(REG_SLV_SCL_LOW_MASK, div_l)); in meson_gxbb_axg_i2c_set_clk_div()
184 clk_rate, freq, div_h, div_l); in meson_gxbb_axg_i2c_set_clk_div()
/drivers/tty/serial/
A Dsunplus-uart.c338 u32 ext, div, div_l, div_h, baud, lcr; in sunplus_set_termios() local
349 div_l = (div & 0xFF) | (ext << 12); in sunplus_set_termios()
409 writel(div_l, port->membase + SUP_UART_DIV_L); in sunplus_set_termios()

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