| /drivers/clk/ |
| A D | clk-loongson2.c | 41 u8 div_shift; member
54 u8 div_shift; member
68 .div_shift = _dshift, \
82 .div_shift = _dshift, \
94 .div_shift = _dshift, \
221 div = loongson2_rate_part(val, clk->div_shift, clk->div_width); in loongson2_pll_recalc_rate()
237 mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; in loongson2_freqscale_recalc_rate()
270 clk->div_shift = cld->div_shift; in loongson2_clk_register()
330 p->div_shift, p->div_width, in loongson2_clk_probe()
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| A D | clk-en7523.c | 59 u8 div_shift; member
108 .div_shift = 0,
122 .div_shift = 0,
136 .div_shift = 0,
163 .div_shift = 8,
177 .div_shift = 0,
204 .div_shift = 0,
218 .div_shift = 0,
232 .div_shift = 0,
259 .div_shift = 8,
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| A D | clk-sp7021.c | 52 int div_shift; member
473 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; in sp_pll_recalc_rate()
498 u32 mask = GENMASK(clk->div_shift + clk->div_width - 1, clk->div_shift); in sp_pll_set_rate()
501 reg |= ((fbdiv - 1) << clk->div_shift) & mask; in sp_pll_set_rate()
576 pll->div_shift = shift; in sp_pll_register()
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| A D | clk-bm1880.c | 120 s8 div_shift; member
152 .div_shift = _div_shift, \
168 .div_shift = -1, \
803 if (clks->div_shift >= 0) { in bm1880_clk_register_composite()
812 div_hws->div.shift = clks->div_shift; in bm1880_clk_register_composite()
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| A D | clk-k210.c | 35 u8 div_shift; member
55 .div_shift = (_shift), \
760 div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0); in k210_clk_get_rate()
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| /drivers/clk/rockchip/ |
| A D | clk.h | 694 u8 div_shift; member
719 .div_shift = ds, \
741 .div_shift = ds, \
759 .div_shift = ds, \
777 .div_shift = ds, \
817 .div_shift = ds, \
836 .div_shift = ds, \
852 .div_shift = 16, \
968 .div_shift = s, \
983 .div_shift = s, \
[all …]
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| A D | clk-ddr.c | 21 int div_shift; member
94 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
129 ddrclk->div_shift = div_shift; in rockchip_clk_register_ddrclk()
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| A D | clk.c | 44 int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
98 div->shift = div_shift; in rockchip_clk_register_branch()
556 list->div_shift, list->div_width, in rockchip_clk_register_branches()
563 list->div_shift, list->div_width, in rockchip_clk_register_branches()
580 list->mux_flags, list->div_shift, in rockchip_clk_register_branches()
607 list->div_shift, list->div_width, in rockchip_clk_register_branches()
618 list->div_shift in rockchip_clk_register_branches()
627 list->div_shift in rockchip_clk_register_branches()
635 list->div_shift, list->div_flags, &ctx->lock); in rockchip_clk_register_branches()
641 list->div_shift, list->div_width, in rockchip_clk_register_branches()
[all …]
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| A D | clk-half-divider.c | 163 u8 div_shift, u8 div_width, in rockchip_clk_register_halfdiv() argument
209 div->shift = div_shift; in rockchip_clk_register_halfdiv()
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| /drivers/clk/x86/ |
| A D | clk-cgu.h | 182 u8 div_shift; member
232 .div_shift = _shift, \
272 .div_shift = _shift, \
292 .div_shift = _shift, \
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| A D | clk-cgu.c | 30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
199 u8 shift = list->div_shift; in lgm_clk_register_divider()
251 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed_factor()
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| /drivers/clk/imx/ |
| A D | clk-pllv3.c | 53 u32 div_shift; member
115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
144 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
145 val |= (div << pll->div_shift); in clk_pllv3_set_rate()
447 pll->div_shift = 1; in imx_clk_hw_pllv3()
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| /drivers/clk/mediatek/ |
| A D | clk-mtk.h | 190 unsigned char div_shift; member
201 .div_shift = _shift, \
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| A D | clk-mt8167-apmixedsys.c | 82 .div_shift = _shift, \
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| A D | clk-mt8516.c | 474 .div_shift = _shift, \
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| A D | clk-mt8167.c | 663 .div_shift = _shift, \
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| A D | clk-mt8365.c | 547 .div_shift = _shift, \
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| /drivers/clk/at91/ |
| A D | clk-sam9x60-pll.c | 351 (div << core->layout->div_shift) | ena_val); in sam9x60_div_pll_set_div()
372 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set()
524 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set_rate_chg()
580 cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; in sam9x60_div_pll_notifier_fn()
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| A D | sam9x7.c | 162 .div_shift = 0,
170 .div_shift = 0,
179 .div_shift = 12,
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| A D | pmc.h | 65 u8 div_shift; member
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| A D | sam9x60.c | 63 .div_shift = 0,
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| A D | sama7d65.c | 84 .div_shift = 0,
92 .div_shift = 12,
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| A D | sama7g5.c | 79 .div_shift = 0,
87 .div_shift = 12,
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| /drivers/mfd/ |
| A D | db8500-prcmu.c | 523 u32 div_shift; member
530 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
535 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
540 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
1534 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
1899 val |= (min(div, (u32)255) << dsiescclk[n].div_shift); in set_dsiescclk_rate()
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| /drivers/clk/tegra/ |
| A D | clk-tegra-periph.c | 832 u8 div_shift; member
843 .div_shift = _div_shift,\
967 data->div_shift, 8, 1, data->lock); in init_pllp()
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