| /drivers/clk/meson/ |
| A D | clk-cpu-dyndiv.c | 47 ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0); in meson_clk_cpu_dyndiv_set_rate()
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| A D | vclk.c | 90 ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width, in meson_vclk_div_set_rate()
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| A D | clk-regmap.c | 156 ret = divider_get_val(rate, parent_rate, div->table, div->width, in clk_regmap_div_set_rate()
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| /drivers/clk/sprd/ |
| A D | div.c | 53 val = divider_get_val(rate, parent_rate, NULL, in sprd_div_helper_set_rate()
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| /drivers/clk/actions/ |
| A D | owl-divider.c | 69 val = divider_get_val(rate, parent_rate, div_hw->table, in owl_divider_helper_set_rate()
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| /drivers/clk/qcom/ |
| A D | clk-regmap-divider.c | 49 div = divider_get_val(rate, parent_rate, NULL, divider->width, in div_set_rate()
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| /drivers/clk/ |
| A D | clk-divider.c | 476 int divider_get_val(unsigned long rate, unsigned long parent_rate, in divider_get_val() function
491 EXPORT_SYMBOL_GPL(divider_get_val);
501 value = divider_get_val(rate, parent_rate, divider->table, in clk_divider_set_rate()
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| A D | clk-loongson1.c | 114 div_val = divider_get_val(rate, parent_rate, d->table, in ls1x_divider_set_rate()
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| A D | clk-milbeaut.c | 419 value = divider_get_val(rate, parent_rate, divider->table, in m10v_clk_divider_set_rate()
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| A D | clk-bm1880.c | 643 value = divider_get_val(rate, parent_rate, div->table, in bm1880_clk_div_set_rate()
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| A D | clk-versaclock3.c | 528 value = divider_get_val(rate, parent_rate, div_data->table, in vc3_div_set_rate()
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| /drivers/clk/hisilicon/ |
| A D | clkdivider-hi6220.c | 75 value = divider_get_val(rate, parent_rate, dclk->table, in hi6220_clkdiv_set_rate()
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| /drivers/clk/nuvoton/ |
| A D | clk-ma35d1-divider.c | 57 value = divider_get_val(rate, parent_rate, dclk->table, in ma35d1_clkdiv_set_rate()
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| /drivers/clk/sunxi-ng/ |
| A D | ccu_div.c | 102 val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width, in ccu_div_set_rate()
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| /drivers/clk/sophgo/ |
| A D | clk-cv18xx-ip.c | 278 val = divider_get_val(rate, parent_rate, NULL, in div_set_rate()
453 val = divider_get_val(rate, parent_rate, NULL, in mux_set_rate()
710 val = divider_get_val(rate, parent_rate, NULL, in mmux_set_rate()
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| A D | clk-sg2042-clkgen.c | 214 value = divider_get_val(rate, parent_rate, NULL, in sg2042_clk_divider_set_rate()
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| A D | clk-sg2044.c | 183 value = divider_get_val(rate, parent_rate, NULL, in sg2044_div_set_rate()
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| /drivers/clk/imx/ |
| A D | clk-divider-gate.c | 82 value = divider_get_val(rate, parent_rate, div->table, in clk_divider_gate_set_rate()
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| A D | clk-composite-93.c | 116 value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags); in imx93_clk_composite_divider_set_rate()
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| /drivers/rtc/ |
| A D | rtc-ac100.c | 229 div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div, in ac100_clkout_set_rate()
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| /drivers/clk/x86/ |
| A D | clk-cgu.c | 152 value = divider_get_val(rate, prate, divider->table, in lgm_clk_divider_set_rate()
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| /drivers/clk/stm32/ |
| A D | clk-stm32-core.c | 239 value = divider_get_val(rate, parent_rate, divider->table, in stm32_divider_set_rate()
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| /drivers/gpu/drm/msm/dsi/phy/ |
| A D | dsi_phy_14nm.c | 655 value = divider_get_val(rate, parent_rate, NULL, postdiv->width, in dsi_pll_14nm_postdiv_set_rate()
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| /drivers/clk/renesas/ |
| A D | rzv2h-cpg.c | 337 value = divider_get_val(rate, parent_rate, divider->table, in rzv2h_ddiv_set_rate()
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| /drivers/clk/nxp/ |
| A D | clk-lpc32xx.c | 984 value = divider_get_val(rate, parent_rate, divider->table, in clk_divider_set_rate()
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