| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_rq_dlg_helpers.c | 125 …(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param) in print__dlg_sys_params_st() argument
129 dml_print("DML_RQ_DLG_CALC: t_mclk_wm_us = %3.2f\n", dlg_sys_param->t_mclk_wm_us); in print__dlg_sys_params_st()
130 dml_print("DML_RQ_DLG_CALC: t_urg_wm_us = %3.2f\n", dlg_sys_param->t_urg_wm_us); in print__dlg_sys_params_st()
131 dml_print("DML_RQ_DLG_CALC: t_sr_wm_us = %3.2f\n", dlg_sys_param->t_sr_wm_us); in print__dlg_sys_params_st()
132 dml_print("DML_RQ_DLG_CALC: t_extra_us = %3.2f\n", dlg_sys_param->t_extra_us); in print__dlg_sys_params_st()
135 dlg_sys_param->deepsleep_dcfclk_mhz); in print__dlg_sys_params_st()
138 dlg_sys_param->total_flip_bw); in print__dlg_sys_params_st()
141 dlg_sys_param->total_flip_bytes); in print__dlg_sys_params_st()
|
| A D | dml1_display_rq_dlg_calc.c | 1001 const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param, in dml1_rq_dlg_get_dlg_params() argument
1162 min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; in dml1_rq_dlg_get_dlg_params()
1164 min_ttu_vblank = dlg_sys_param->t_urg_wm_us; in dml1_rq_dlg_get_dlg_params()
1166 min_ttu_vblank = dml_max(dlg_sys_param->t_sr_wm_us, min_ttu_vblank); in dml1_rq_dlg_get_dlg_params()
1168 min_ttu_vblank = dml_max(dlg_sys_param->t_mclk_wm_us, min_ttu_vblank); in dml1_rq_dlg_get_dlg_params()
1406 flip_bw = ((vm_bytes + dpte_row_bytes + meta_row_bytes) * dlg_sys_param->total_flip_bw) in dml1_rq_dlg_get_dlg_params()
1407 / (double) dlg_sys_param->total_flip_bytes; in dml1_rq_dlg_get_dlg_params()
1411 dlg_sys_param->t_extra_us, in dml1_rq_dlg_get_dlg_params()
1421 t_r0_us = dml_max(dlg_sys_param->t_extra_us - t_vm_us, line_time_in_us - t_vm_us); in dml1_rq_dlg_get_dlg_params()
1426 dlg_sys_param->t_extra_us); in dml1_rq_dlg_get_dlg_params()
|
| A D | dml1_display_rq_dlg_calc.h | 59 const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param,
|
| A D | display_rq_dlg_helpers.h | 38 …struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param);
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 53 const display_dlg_sys_params_st *dlg_sys_param,
783 const display_dlg_sys_params_st *dlg_sys_param, in dml20_rq_dlg_get_dlg_params() argument
929 min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; in dml20_rq_dlg_get_dlg_params()
1542 display_dlg_sys_params_st dlg_sys_param = {0}; in dml20_rq_dlg_get_dlg_reg() local
1545 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_reg()
1546 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, in dml20_rq_dlg_get_dlg_reg()
1550 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_reg()
1553 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, in dml20_rq_dlg_get_dlg_reg()
1556 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, in dml20_rq_dlg_get_dlg_reg()
1560 print__dlg_sys_params_st(mode_lib, &dlg_sys_param); in dml20_rq_dlg_get_dlg_reg()
[all …]
|
| A D | display_rq_dlg_calc_20v2.c | 53 const display_dlg_sys_params_st *dlg_sys_param,
783 const display_dlg_sys_params_st *dlg_sys_param, in dml20v2_rq_dlg_get_dlg_params() argument
929 min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; in dml20v2_rq_dlg_get_dlg_params()
1543 display_dlg_sys_params_st dlg_sys_param = {0}; in dml20v2_rq_dlg_get_dlg_reg() local
1546 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
1547 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, in dml20v2_rq_dlg_get_dlg_reg()
1551 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
1554 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, in dml20v2_rq_dlg_get_dlg_reg()
1557 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, in dml20v2_rq_dlg_get_dlg_reg()
1561 print__dlg_sys_params_st(mode_lib, &dlg_sys_param); in dml20v2_rq_dlg_get_dlg_reg()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 829 const display_dlg_sys_params_st *dlg_sys_param, in dml_rq_dlg_get_dlg_params() argument
975 min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; in dml_rq_dlg_get_dlg_params()
1651 display_dlg_sys_params_st dlg_sys_param = {0}; in dml21_rq_dlg_get_dlg_reg() local
1654 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml21_rq_dlg_get_dlg_reg()
1655 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep( in dml21_rq_dlg_get_dlg_reg()
1659 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); in dml21_rq_dlg_get_dlg_reg()
1660 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml21_rq_dlg_get_dlg_reg()
1663 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw( in dml21_rq_dlg_get_dlg_reg()
1667 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes( in dml21_rq_dlg_get_dlg_reg()
1672 print__dlg_sys_params_st(mode_lib, &dlg_sys_param); in dml21_rq_dlg_get_dlg_reg()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 892 const display_dlg_sys_params_st dlg_sys_param, in dml_rq_dlg_get_dlg_params() argument
1043 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; in dml_rq_dlg_get_dlg_params()
1739 display_dlg_sys_params_st dlg_sys_param = { 0 }; in dml30_rq_dlg_get_dlg_reg() local
1742 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml30_rq_dlg_get_dlg_reg()
1743 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, in dml30_rq_dlg_get_dlg_reg()
1746 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); in dml30_rq_dlg_get_dlg_reg()
1747 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml30_rq_dlg_get_dlg_reg()
1750 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, in dml30_rq_dlg_get_dlg_reg()
1753 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, in dml30_rq_dlg_get_dlg_reg()
1757 print__dlg_sys_params_st(mode_lib, &dlg_sys_param); in dml30_rq_dlg_get_dlg_reg()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 855 const display_dlg_sys_params_st *dlg_sys_param, in dml_rq_dlg_get_dlg_params() argument
1557 display_dlg_sys_params_st dlg_sys_param = {0}; in dml31_rq_dlg_get_dlg_reg() local
1560 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1561 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1562 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1563 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1564 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1565 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1566 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1569 print__dlg_sys_params_st(mode_lib, &dlg_sys_param); in dml31_rq_dlg_get_dlg_reg()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.c | 940 const display_dlg_sys_params_st *dlg_sys_param, in dml_rq_dlg_get_dlg_params() argument
1645 display_dlg_sys_params_st dlg_sys_param = {0}; in dml314_rq_dlg_get_dlg_reg() local
1648 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1649 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1650 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1651 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1652 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1653 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1654 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1657 print__dlg_sys_params_st(mode_lib, &dlg_sys_param); in dml314_rq_dlg_get_dlg_reg()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 463 struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param = &pipe->dml_dlg_sys_param; in dcn_bw_calc_rq_dlg_ttu() local
474 memset(dlg_sys_param, 0, sizeof(*dlg_sys_param)); in dcn_bw_calc_rq_dlg_ttu()
483 if (dlg_sys_param->total_flip_bw < 0.0) in dcn_bw_calc_rq_dlg_ttu()
484 dlg_sys_param->total_flip_bw = 0; in dcn_bw_calc_rq_dlg_ttu()
486 dlg_sys_param->t_mclk_wm_us = v->dram_clock_change_watermark; in dcn_bw_calc_rq_dlg_ttu()
487 dlg_sys_param->t_sr_wm_us = v->stutter_enter_plus_exit_watermark; in dcn_bw_calc_rq_dlg_ttu()
488 dlg_sys_param->t_urg_wm_us = v->urgent_watermark; in dcn_bw_calc_rq_dlg_ttu()
489 dlg_sys_param->t_extra_us = v->urgent_extra_latency; in dcn_bw_calc_rq_dlg_ttu()
490 dlg_sys_param->deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep; in dcn_bw_calc_rq_dlg_ttu()
491 dlg_sys_param->total_flip_bytes = total_flip_bytes; in dcn_bw_calc_rq_dlg_ttu()
[all …]
|