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Searched refs:dm_read_reg (Results 1 – 25 of 29) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_compressor.c119 value = dm_read_reg(cp110->base.ctx, addr); in wait_for_fbc_state_changed()
145 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
160 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
167 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
198 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_enable_fbc()
247 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce110_compressor_disable_fbc()
272 value = dm_read_reg(compressor->ctx, mmFBC_STATUS); in dce110_compressor_is_fbc_enabled_in_hw()
279 value = dm_read_reg(compressor->ctx, mmFBC_MISC); in dce110_compressor_is_fbc_enabled_in_hw()
281 value = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce110_compressor_is_fbc_enabled_in_hw()
351 uint32_t value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_set_fbc_invalidation_triggers()
[all …]
A Ddce110_mem_input_v.c45 value = dm_read_reg( in set_flip_control()
369 value = dm_read_reg( in program_pixel_format()
422 value = dm_read_reg( in program_pixel_format()
442 value = dm_read_reg( in program_pixel_format()
665 wm_mask_cntl = dm_read_reg(ctx, wm_addr); in program_urgency_watermark()
688 wm_mask_cntl = dm_read_reg(ctx, wm_addr); in program_urgency_watermark()
748 wm_mask_cntl = dm_read_reg(ctx, wm_addr); in program_stutter_watermark()
782 wm_mask_cntl = dm_read_reg(ctx, wm_addr); in program_stutter_watermark()
828 value = dm_read_reg(ctx, wm_mask_ctrl_addr); in program_nbp_watermark()
978 value = dm_read_reg(mi->ctx, addr); in dce110_allocate_mem_input_v()
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A Ddce110_timing_generator_v.c84 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
102 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
147 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_is_in_vertical_blank()
259 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
268 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
277 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
300 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
331 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
357 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
374 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
[all …]
A Ddce110_timing_generator.c100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
113 regval = dm_read_reg(tg->ctx, address); in dce110_timing_generator_set_early_control()
199 value = dm_read_reg(tg->ctx, addr);
261 regval = dm_read_reg(tg->ctx, in program_horz_count_by_2()
619 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
628 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
640 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
649 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
658 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
681 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
[all …]
A Ddce110_opp_regamma_v.c37 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
71 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
88 value = dm_read_reg(xfm_dce->base.ctx, in set_bypass_input_gamma()
521 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in dce110_opp_power_on_regamma_lut_v()
A Ddce110_opp_csc_v.c114 uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL); in program_color_matrix_v()
366 uint32_t value = dm_read_reg(ctx, addr); in configure_graphics_mode_v()
465 uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL); in set_Denormalization()
555 value = dm_read_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL); in program_input_csc()
A Ddce110_transform_v.c277 value = dm_read_reg(xfm_dce->base.ctx, mmSCLV_UPDATE); in set_coeff_update_complete()
301 power_ctl = dm_read_reg(ctx, mmDCFEV_MEM_PWR_CTRL); in program_multi_taps_filter()
309 dm_read_reg(ctx, mmDCFEV_MEM_PWR_STATUS), in program_multi_taps_filter()
508 value = dm_read_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL); in dce110_xfmv_power_up_line_buffer()
/drivers/gpu/drm/amd/display/dc/dce112/
A Ddce112_compressor.c299 value = dm_read_reg(cp110->base.ctx, addr); in wait_for_fbc_state_changed()
322 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
337 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
344 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
550 dm_read_reg( in dce112_compressor_disable_lpt()
565 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_disable_lpt()
575 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_disable_lpt()
585 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_disable_lpt()
603 value = dm_read_reg(compressor->ctx, in dce112_compressor_enable_lpt()
615 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_enable_lpt()
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/drivers/gpu/drm/amd/display/dc/irq/
A Dirq_service.c101 uint32_t value = dm_read_reg(irq_service->ctx, addr); in dal_irq_service_set_generic()
145 uint32_t value = dm_read_reg(irq_service->ctx, addr); in dal_irq_service_ack_generic()
196 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd0_ack()
205 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd0_ack()
223 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd1_ack()
232 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd1_ack()
/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_timing_generator.c92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
131 uint32_t value = dm_read_reg(tg->ctx, addr); in dce60_timing_generator_enable_advanced_request()
134 uint32_t value2 = dm_read_reg(tg->ctx, addr2); in dce60_timing_generator_enable_advanced_request()
187 value = dm_read_reg(tg->ctx, addr); in dce60_is_tg_enabled()
/drivers/gpu/drm/amd/display/dc/
A Ddc_helper.c243 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex()
280 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get()
289 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get2()
300 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get3()
313 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get4()
328 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get5()
345 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get6()
364 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get7()
385 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get8()
459 reg_val = dm_read_reg(ctx, addr); in generic_reg_wait()
[all …]
A Ddm_services.h65 #define dm_read_reg(ctx, address) \ macro
/drivers/net/usb/
A Ddm9601.c72 static int dm_read_reg(struct usbnet *dev, u8 reg, u8 *value) in dm_read_reg() function
124 ret = dm_read_reg(dev, DM_SHARED_CTRL, &tmp); in dm_read_shared_word()
167 ret = dm_read_reg(dev, DM_SHARED_CTRL, &tmp); in dm_write_shared_word()
408 if (dm_read_reg(dev, DM_CHIP_ID, &id) < 0) { in dm9601_bind()
418 if (dm_read_reg(dev, DM_MODE_CTRL, &mode) < 0) { in dm9601_bind()
/drivers/gpu/drm/amd/display/dc/dce80/
A Ddce80_timing_generator.c92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
131 uint32_t value = dm_read_reg(tg->ctx, addr); in dce80_timing_generator_enable_advanced_request()
/drivers/gpu/drm/amd/display/dc/irq/dce110/
A Dirq_service_dce110.c46 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
53 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
/drivers/gpu/drm/amd/display/dc/hwss/dce112/
A Ddce112_hwseq.c77 value = dm_read_reg(ctx, addr); in dce112_init_pte()
/drivers/gpu/drm/amd/display/dc/hwss/dce120/
A Ddce120_hwseq.c114 value = dm_read_reg(ctx, addr);
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_link_encoder.c630 uint32_t value = dm_read_reg(ctx, addr); in aux_initialize()
637 value = dm_read_reg(ctx, addr); in aux_initialize()
1647 uint32_t value = dm_read_reg(ctx, addr); in dce110_link_encoder_enable_hpd()
1660 uint32_t value = dm_read_reg(ctx, addr); in dce110_link_encoder_disable_hpd()
/drivers/gpu/drm/amd/display/dc/dio/dcn321/
A Ddcn321_dio_link_encoder.c57 dm_read_reg(CTX, AUX_REG(reg_name))
/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_link_encoder.c212 dm_read_reg(CTX, AUX_REG(reg_name))
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_link_encoder.c60 dm_read_reg(CTX, AUX_REG(reg_name))
/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_link_encoder.c59 dm_read_reg(CTX, AUX_REG(reg_name))
/drivers/gpu/drm/amd/display/dc/dio/dcn20/
A Ddcn20_link_encoder.c304 dm_read_reg(CTX, AUX_REG(reg_name))
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_link_encoder.c1370 dm_read_reg(CTX, HPD_REG(reg_name))
1401 dm_read_reg(CTX, AUX_REG(reg_name))
/drivers/gpu/drm/amd/display/dc/dio/dcn31/
A Ddcn31_dio_link_encoder.c61 dm_read_reg(CTX, AUX_REG(reg_name))

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