Searched refs:dmar_writeq (Results 1 – 6 of 6) sorted by relevance
| /drivers/iommu/intel/ |
| A D | prq.c | 263 dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); in prq_event_thread()
329 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_iommu_enable_prq()
330 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_iommu_enable_prq()
331 dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER); in intel_iommu_enable_prq()
352 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_iommu_finish_prq()
353 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_iommu_finish_prq()
354 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); in intel_iommu_finish_prq()
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| A D | perfmon.c | 414 dmar_writeq(iommu_config_base(iommu_pmu, idx), hwc->config); in iommu_pmu_assign_event()
513 dmar_writeq(iommu_pmu->overflow, status); in iommu_pmu_counter_overflow()
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| A D | iommu.c | 1013 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); in iommu_set_root_entry()
1081 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); in __iommu_flush_context()
1122 dmar_writeq(iommu->reg + tlb_offset, val_iva); in __iommu_flush_iotlb()
1123 dmar_writeq(iommu->reg + tlb_offset + 8, val); in __iommu_flush_iotlb()
4778 dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob); in ecmd_submit_sync()
4779 dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT)); in ecmd_submit_sync()
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| A D | iommu.h | 153 #define dmar_writeq(a,v) writeq(v,a) macro
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| A D | irq_remapping.c | 468 dmar_writeq(iommu->reg + DMAR_IRTA_REG, in iommu_set_irq_remapping()
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| A D | dmar.c | 1665 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); in __dmar_enable_qi()
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