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Searched refs:dml (Results 1 – 25 of 46) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dml/
A DMakefile43 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
44 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
45 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
46 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
60 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags)
61 CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/dcn32_fpu.o := $(dml_ccflags)
66 CFLAGS_$(AMDDALPATH)/dc/dml/dcn35/dcn35_fpu.o := $(dml_ccflags)
68 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags)
72 CFLAGS_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_ccflags)
73 CFLAGS_$(AMDDALPATH)/dc/dml/calcs/dcn_calcs.o := $(dml_ccflags)
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml2_top_soc15.c215 if (!params->dml || in dml2_top_optimization_perform_optimization_phase()
225 init_params.dml = params->dml; in dml2_top_optimization_perform_optimization_phase()
232 test_params.dml = params->dml; in dml2_top_optimization_perform_optimization_phase()
241 optimize_params.dml = params->dml; in dml2_top_optimization_perform_optimization_phase()
264 test_params.dml = params->dml; in dml2_top_optimization_perform_optimization_phase()
796 .dml = dml, in dml2_top_soc15_check_mode_supported()
873 l->min_clock_for_latency_phase.dml = dml; in dml2_top_soc15_build_mode_programming()
890 l->mcache_phase.dml = dml; in dml2_top_soc15_build_mode_programming()
916 l->uclk_pstate_phase.dml = dml; in dml2_top_soc15_build_mode_programming()
935 l->vmin_phase.dml = dml; in dml2_top_soc15_build_mode_programming()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c218 if (dc->dml.ip.writeback_max_hscl_taps > 1) { in dcn30_fpu_populate_dml_writeback_from_context()
272 struct display_mode_lib *dml, in dcn30_fpu_set_mcif_arb_params() argument
344 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
345 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
350 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn30_fpu_calculate_wm_and_dlg()
351 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
499 dc->dml.soc.num_chans <= 4 && in dcn30_fpu_calculate_wm_and_dlg()
500 context->bw_ctx.dml.vba.DRAMSpeed <= 1700 && in dcn30_fpu_calculate_wm_and_dlg()
501 context->bw_ctx.dml.vba.DRAMSpeed >= 1500) { in dcn30_fpu_calculate_wm_and_dlg()
503 for (i = 0; i < dc->dml.soc.num_states; i++) { in dcn30_fpu_calculate_wm_and_dlg()
[all …]
A Ddcn30_fpu.h36 struct display_mode_lib *dml,
/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c295 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel() argument
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
307 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
308 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; in calculate_wm_set_for_vlevel()
311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
435 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
440 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
445 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
475 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn315_update_soc_for_wm_a()
477 context->bw_ctx.dml.soc.sr_exit_time_us = in dcn315_update_soc_for_wm_a()
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
494 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()
495 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn31_calculate_wm_and_dlg_fp()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
665 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); in dcn31_update_bw_bounding_box()
798 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn316_update_bw_bounding_box()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1165 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1226 …bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] … in dcn20_calculate_dlg_params()
1235 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, in dcn20_calculate_dlg_params()
1245 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, in dcn20_calculate_dlg_params()
1751 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn20_calculate_wm()
1760 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from… in dcn20_calculate_wm()
2067 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn20_validate_bandwidth_internal()
2112 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn20_validate_bandwidth_fp()
2209 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel() argument
2215 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c479 …unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcCo… in dcn32_set_phantom_stream_timing()
1417 context->bw_ctx.dml.vba.VoltageLevel = *vlevel; in try_odm_power_optimization_and_revalidate()
1666 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn32_calculate_dlg_params()
1677 …if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fc… in dcn32_calculate_dlg_params()
1682 …usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.… in dcn32_calculate_dlg_params()
1799 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, in dcn32_calculate_dlg_params()
2150 int vlevel = context->bw_ctx.dml.soc.num_states; in dcn32_internal_validate_bw()
2309 …double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vb… in dcn32_calculate_wm_and_dlg_fpu()
2312 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.ma… in dcn32_calculate_wm_and_dlg_fpu()
2399 …cfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.d… in dcn32_calculate_wm_and_dlg_fpu()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu() local
508 dml1_extract_rq_regs(dml, rq_regs, rq_param); in dcn_bw_calc_rq_dlg_ttu()
510 dml, in dcn_bw_calc_rq_dlg_ttu()
1294 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn_validate_bandwidth()
1572 dc->dml.soc.ideal_dram_bw_after_urgent_percent = in dcn_bw_sync_calcs_and_dml()
1576 dc->dml.soc.round_trip_ping_latency_dcfclk_cycles = in dcn_bw_sync_calcs_and_dml()
1600 dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp; in dcn_bw_sync_calcs_and_dml()
1601 dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback; in dcn_bw_sync_calcs_and_dml()
1608 dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps; in dcn_bw_sync_calcs_and_dml()
1609 dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps; in dcn_bw_sync_calcs_and_dml()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c265 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn314_update_bw_bounding_box_fpu()
269 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314); in dcn314_update_bw_bounding_box_fpu()
392 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; in dcn314_populate_dml_pipes_from_context_fpu()
402 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
407 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn314_populate_dml_pipes_from_context_fpu()
409 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
413 context->bw_ctx.dml.ip.odm_combine_4to1_supported = true; in dcn314_populate_dml_pipes_from_context_fpu()
425 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; in dcn314_populate_dml_pipes_from_context_fpu()
/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c321 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn35_update_bw_bounding_box_fpu()
349 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, in dcn35_update_bw_bounding_box_fpu()
530 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn35_populate_dml_pipes_from_context_fpu()
544 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
550 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn35_populate_dml_pipes_from_context_fpu()
553 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
568 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn35_populate_dml_pipes_from_context_fpu()
599 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn35_decide_zstate_support()
602 bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency; in dcn35_decide_zstate_support()
615 (int)context->bw_ctx.dml.vba.StutterPeriod); in dcn35_decide_zstate_support()
/drivers/gpu/drm/amd/display/dc/dml/dcn10/
A Ddcn10_fpu.c133 struct display_mode_lib *dml = &dc->dml; in dcn10_resource_construct_fp() local
135 dml->ip.max_num_dpp = 3; in dcn10_resource_construct_fp()
/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c355 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn351_update_bw_bounding_box_fpu()
383 dml_init_instance(&dc->dml, &dcn3_51_soc, &dcn3_51_ip, in dcn351_update_bw_bounding_box_fpu()
563 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn351_populate_dml_pipes_from_context_fpu()
577 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
583 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn351_populate_dml_pipes_from_context_fpu()
586 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
601 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn351_populate_dml_pipes_from_context_fpu()
632 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn351_decide_zstate_support()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_translation_helper.c612 const struct _vcs_dpi_ip_params_st *in_ip_params = &in->dml.ip; in dml2_translate_ip_params()
681 const struct _vcs_dpi_soc_bounding_box_st *in_soc_params = &in->dml.soc; in dml2_translate_socbb_params()
719 out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz; in dml2_translate_soc_states()
720 out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz; in dml2_translate_soc_states()
721 out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz; in dml2_translate_soc_states()
723 out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz; in dml2_translate_soc_states()
724 out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz; in dml2_translate_soc_states()
726 out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz; in dml2_translate_soc_states()
729 out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz; in dml2_translate_soc_states()
731 out->state_array[i].sr_exit_time_us = dc->dml.soc.sr_exit_time_us; in dml2_translate_soc_states()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c1380 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params() local
1639 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1645 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1646 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1668 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1686 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1691 context->bw_ctx.dml.validate_max_state = false; in dcn30_internal_validate_bw()
1694 dml_log_mode_support_params(&context->bw_ctx.dml); in dcn30_internal_validate_bw()
1696 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1869 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn21/
A Ddcn21_resource.c800 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
802 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
804 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
812 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
814 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
815 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
824 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
878 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
882 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
904 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
[all …]
/drivers/gpu/drm/amd/display/dc/
A DMakefile25 DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc dpp hubbub dccg …
38 DC_LIBS += dml
/drivers/gpu/drm/amd/display/dc/dml/dcn302/
A Ddcn302_fpu.c218 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn302_fpu_update_bw_bounding_box()
343 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_fpu_update_bw_bounding_box()
345 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_fpu_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
A Ddml2_internal_shared_types.h874 struct dml2_instance *dml; member
880 struct dml2_instance *dml; member
887 struct dml2_instance *dml; member
893 struct dml2_instance *dml; member
/drivers/gpu/drm/amd/display/dc/dml/dcn303/
A Ddcn303_fpu.c214 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn303_fpu_update_bw_bounding_box()
362 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_fpu_update_bw_bounding_box()
364 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_fpu_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1826 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
1881 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1886 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2034 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
2036 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2054 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2073 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2083 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2087 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2110 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn315/
A Ddcn315_resource.c1672 …const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MI… in dcn315_populate_dml_pipes_from_context()
1705 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB); in dcn315_populate_dml_pipes_from_context()
1709 …ired = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); in dcn315_populate_dml_pipes_from_context()
1758 …t_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) in dcn315_populate_dml_pipes_from_context()
1783 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn315_populate_dml_pipes_from_context()
1785 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) in dcn315_populate_dml_pipes_from_context()
1786 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; in dcn315_populate_dml_pipes_from_context()
1793 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn315_populate_dml_pipes_from_context()
1797 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { in dcn315_populate_dml_pipes_from_context()
1799 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn315_populate_dml_pipes_from_context()
/drivers/gpu/drm/amd/display/dc/resource/dcn316/
A Ddcn316_resource.c1618 …const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MI… in dcn316_populate_dml_pipes_from_context()
1668 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn316_populate_dml_pipes_from_context()
1670 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE) in dcn316_populate_dml_pipes_from_context()
1671 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE; in dcn316_populate_dml_pipes_from_context()
1672 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE); in dcn316_populate_dml_pipes_from_context()
1678 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn316_populate_dml_pipes_from_context()
1681 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn316_populate_dml_pipes_from_context()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c869 ctx->dc->dml.ip.det_buffer_size_kbytes, in dcn32_hubbub_create()
870 ctx->dc->dml.ip.pixel_chunk_size_kbytes, in dcn32_hubbub_create()
871 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); in dcn32_hubbub_create()
1760 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; in dml1_validate()
1797 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dml1_validate()
2016 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; in dcn32_populate_dml_pipes_from_context()
2018 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; in dcn32_populate_dml_pipes_from_context()
2355 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); in dcn32_resource_construct()
/drivers/gpu/drm/amd/display/dc/resource/dcn31/
A Ddcn31_resource.c1702 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; in dcn31_populate_dml_pipes_from_context()
1710 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn31_populate_dml_pipes_from_context()
1715 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn31_populate_dml_pipes_from_context()
1717 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn31_populate_dml_pipes_from_context()
1726 return context->bw_ctx.dml.ip.det_buffer_size_kbytes; in dcn31_get_det_buffer_size()
1806 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn31_validate_bandwidth()

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