| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 390 dc->dml2_options.bbox_overrides.clks_table.num_states = in dcn351_update_bw_bounding_box_fpu()
392 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = in dcn351_update_bw_bounding_box_fpu()
394 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = in dcn351_update_bw_bounding_box_fpu()
396 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz = in dcn351_update_bw_bounding_box_fpu()
398 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz = in dcn351_update_bw_bounding_box_fpu()
400 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz = in dcn351_update_bw_bounding_box_fpu()
402 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz = in dcn351_update_bw_bounding_box_fpu()
405 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz = in dcn351_update_bw_bounding_box_fpu()
407 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn351_update_bw_bounding_box_fpu()
409 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn351_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 356 dc->dml2_options.bbox_overrides.clks_table.num_states = in dcn35_update_bw_bounding_box_fpu()
358 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu()
360 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = in dcn35_update_bw_bounding_box_fpu()
362 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz = in dcn35_update_bw_bounding_box_fpu()
364 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz = in dcn35_update_bw_bounding_box_fpu()
366 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz = in dcn35_update_bw_bounding_box_fpu()
368 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz = in dcn35_update_bw_bounding_box_fpu()
372 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz = in dcn35_update_bw_bounding_box_fpu()
376 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn35_update_bw_bounding_box_fpu()
394 dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_5_soc.sr_exit_time_us; in dcn35_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| A D | dcn321_fpu.c | 619 dc->dml2_options.bbox_overrides.sr_exit_latency_us = in dcn321_update_bw_bounding_box_fpu()
626 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = in dcn321_update_bw_bounding_box_fpu()
634 dc->dml2_options.bbox_overrides.urgent_latency_us = in dcn321_update_bw_bounding_box_fpu()
641 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
649 dc->dml2_options.bbox_overrides.fclk_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
667 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
672 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = in dcn321_update_bw_bounding_box_fpu()
677 dc->dml2_options.bbox_overrides.sr_exit_latency_us = in dcn321_update_bw_bounding_box_fpu()
685 dc->dml2_options.bbox_overrides.dram_num_chan = in dcn321_update_bw_bounding_box_fpu()
692 dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = in dcn321_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 1588 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); in dcn321_update_bw_bounding_box()
2017 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn321_resource_construct()
2018 dc->dml2_options.use_native_soc_bb_construction = true; in dcn321_resource_construct()
2019 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn321_resource_construct()
2021 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn321_resource_construct()
2023 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; in dcn321_resource_construct()
2035 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; in dcn321_resource_construct()
2039 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; in dcn321_resource_construct()
2040 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; in dcn321_resource_construct()
2042 dc->dml2_options.max_segments_per_hubp = 18; in dcn321_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 1621 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); in dcn401_update_bw_bounding_box()
2212 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn401_resource_construct()
2213 dc->dml2_options.use_native_soc_bb_construction = true; in dcn401_resource_construct()
2214 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn401_resource_construct()
2215 dc->dml2_options.map_dc_pipes_with_callbacks = true; in dcn401_resource_construct()
2216 dc->dml2_options.force_tdlut_enable = true; in dcn401_resource_construct()
2218 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn401_resource_construct()
2232 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; in dcn401_resource_construct()
2237 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; in dcn401_resource_construct()
2239 dc->dml2_options.max_segments_per_hubp = 20; in dcn401_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 2069 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); in dcn32_update_bw_bounding_box()
2518 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn32_resource_construct()
2519 dc->dml2_options.use_native_soc_bb_construction = true; in dcn32_resource_construct()
2520 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn32_resource_construct()
2522 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn32_resource_construct()
2524 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; in dcn32_resource_construct()
2536 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; in dcn32_resource_construct()
2541 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; in dcn32_resource_construct()
2543 dc->dml2_options.max_segments_per_hubp = 18; in dcn32_resource_construct()
2544 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE; in dcn32_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 5540 dml2_options->callbacks.dc = dc; in resource_init_common_dml2_callbacks()
5541 dml2_options->callbacks.build_scaling_params = &resource_build_scaling_params; in resource_init_common_dml2_callbacks()
5546 dml2_options->callbacks.get_mpc_slice_index = &resource_get_mpc_slice_index; in resource_init_common_dml2_callbacks()
5547 dml2_options->callbacks.get_mpc_slice_count = &resource_get_mpc_slice_count; in resource_init_common_dml2_callbacks()
5548 dml2_options->callbacks.get_odm_slice_index = &resource_get_odm_slice_index; in resource_init_common_dml2_callbacks()
5549 dml2_options->callbacks.get_odm_slice_count = &resource_get_odm_slice_count; in resource_init_common_dml2_callbacks()
5550 dml2_options->callbacks.get_opp_head = &resource_get_opp_head; in resource_init_common_dml2_callbacks()
5554 dml2_options->callbacks.get_stream_status = &dc_state_get_stream_status; in resource_init_common_dml2_callbacks()
5555 dml2_options->callbacks.get_stream_from_id = &dc_state_get_stream_from_id; in resource_init_common_dml2_callbacks()
5557 dml2_options->callbacks.allocate_mcache = &resource_allocate_mcache; in resource_init_common_dml2_callbacks()
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| A D | dc_vm_helper.c | 50 dc->dml2_options.gpuvm_enable = true; in dc_setup_system_context()
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| A D | dc_state.c | 209 if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) { in dc_state_create()
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| A D | dc.c | 1074 dc->dml2_options.bb_from_dmub = init_params->bb_from_dmub; in dc_construct()
1076 dc->dml2_options.bb_from_dmub = NULL; in dc_construct()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 3061 dc->dml2_options.bbox_overrides.sr_exit_latency_us = in dcn32_update_bw_bounding_box_fpu()
3068 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = in dcn32_update_bw_bounding_box_fpu()
3076 dc->dml2_options.bbox_overrides.urgent_latency_us = in dcn32_update_bw_bounding_box_fpu()
3083 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
3091 dc->dml2_options.bbox_overrides.fclk_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
3109 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
3114 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = in dcn32_update_bw_bounding_box_fpu()
3119 dc->dml2_options.bbox_overrides.sr_exit_latency_us = in dcn32_update_bw_bounding_box_fpu()
3127 dc->dml2_options.bbox_overrides.dram_num_chan = in dcn32_update_bw_bounding_box_fpu()
3134 dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = in dcn32_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 2166 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn35_resource_construct()
2167 dc->dml2_options.use_native_soc_bb_construction = true; in dcn35_resource_construct()
2168 dc->dml2_options.minimize_dispclk_using_odm = false; in dcn35_resource_construct()
2170 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn35_resource_construct()
2171 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; in dcn35_resource_construct()
2173 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn35_resource_construct()
2174 …dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_supp… in dcn35_resource_construct()
2176 dc->dml2_options.max_segments_per_hubp = 24; in dcn35_resource_construct()
2177 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ in dcn35_resource_construct()
2178 dc->dml2_options.override_det_buffer_size_kbytes = true; in dcn35_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 2138 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn351_resource_construct()
2139 dc->dml2_options.use_native_soc_bb_construction = true; in dcn351_resource_construct()
2140 dc->dml2_options.minimize_dispclk_using_odm = false; in dcn351_resource_construct()
2142 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn351_resource_construct()
2143 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; in dcn351_resource_construct()
2145 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn351_resource_construct()
2146 …dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_supp… in dcn351_resource_construct()
2148 dc->dml2_options.max_segments_per_hubp = 24; in dcn351_resource_construct()
2149 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ in dcn351_resource_construct()
2150 dc->dml2_options.override_det_buffer_size_kbytes = true; in dcn351_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 2139 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn36_resource_construct()
2140 dc->dml2_options.use_native_soc_bb_construction = true; in dcn36_resource_construct()
2141 dc->dml2_options.minimize_dispclk_using_odm = false; in dcn36_resource_construct()
2143 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn36_resource_construct()
2144 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; in dcn36_resource_construct()
2146 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn36_resource_construct()
2147 …dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_supp… in dcn36_resource_construct()
2149 dc->dml2_options.max_segments_per_hubp = 24; in dcn36_resource_construct()
2150 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ in dcn36_resource_construct()
2151 dc->dml2_options.override_det_buffer_size_kbytes = true; in dcn36_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_types.h | 75 struct dml2_options { struct
82 struct dml2_options options; argument
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | resource.h | 648 …esource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options);
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc.h | 1733 struct dml2_configuration_options dml2_options; member
|