| /drivers/gpu/drm/i915/display/ |
| A D | intel_dpll.c | 38 } dot, vco, n, m, m1, m2, p, p1; member
46 .dot = { .min = 25000, .max = 350000 },
325 clock->dot = clock->p == 0 ? 0 : in pnv_calc_dpll_params()
328 return clock->dot; in pnv_calc_dpll_params()
343 clock->dot = clock->p == 0 ? 0 : in i9xx_calc_dpll_params()
346 return clock->dot; in i9xx_calc_dpll_params()
356 clock->dot = clock->p == 0 ? 0 : in vlv_calc_dpll_params()
359 return clock->dot; in vlv_calc_dpll_params()
369 clock->dot = clock->p == 0 ? 0 : in chv_calc_dpll_params()
372 return clock->dot; in chv_calc_dpll_params()
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| A D | g4x_dp.c | 36 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
37 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
41 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
42 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
46 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
47 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
52 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
53 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
84 if (pipe_config->port_clock == divisor[i].dot) { in g4x_dp_set_clock()
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| A D | intel_dpll_mgr.c | 2246 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2247 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
2248 { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
2249 { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2250 { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6133333 /* 24.3 */ },
2251 { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2252 { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2282 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2291 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
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| A D | intel_display_types.h | 585 int dot; member
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| A D | intel_display.c | 8231 pipe_name(pipe), clock.vco, clock.dot); in i830_enable_pipe()
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| /drivers/gpu/drm/gma500/ |
| A D | cdv_intel_display.c | 37 .dot = {.min = 20000, .max = 115500},
49 .dot = {.min = 20000, .max = 115500},
64 .dot = {.min = 20000, .max = 400000},
76 .dot = {.min = 20000, .max = 400000},
88 .dot = {.min = 160000, .max = 272000},
100 .dot = {.min = 160000, .max = 272000},
398 clock->dot = clock->vco / clock->p; in cdv_intel_clock()
661 adjusted_mode->clock, clock.dot); in cdv_intel_crtc_mode_set()
831 clock->dot = clock->vco / clock->p; in i8xx_clock()
910 return clock.dot; in cdv_intel_crtc_clock_get()
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| A D | gma_display.h | 25 int dot; member
41 struct gma_range_t dot, vco, n, m, m1, m2, p, p1; member
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| A D | oaktrail_crtc.c | 49 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
55 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
61 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
116 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
122 clock->dot, clock->m, clock->m1, clock->m2, clock->n, in mrst_print_pll()
201 this_err = abs(clock.dot - target); in mrst_lvds_find_best_pll()
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| A D | psb_intel_display.c | 28 .dot = {.min = 20000, .max = 400000},
40 .dot = {.min = 20000, .max = 400000},
73 clock->dot = clock->vco / clock->p; in psb_intel_clock()
152 adjusted_mode->clock, clock.dot); in psb_intel_crtc_mode_set()
375 return clock.dot; in psb_intel_crtc_clock_get()
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| A D | gma_display.c | 744 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in gma_pll_is_valid()
800 this_err = abs(clock.dot - target); in gma_find_best_pll()
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| A D | oaktrail_hdmi.c | 115 int dot; member
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| /drivers/gpu/drm/i915/gvt/ |
| A D | handlers.c | 605 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); in bxt_vgpu_get_dp_bitrate()
607 dp_br = clock.dot; in bxt_vgpu_get_dp_bitrate()
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| /drivers/gpu/drm/panel/ |
| A D | Kconfig | 301 WXGA MIPI DSI panel. The panel support TFT dot matrix LCD with
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