Searched refs:dp_phy (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | intel_dp_link_training.c | 73 enum drm_dp_phy dp_phy) in intel_dp_lttpr_phy_caps() argument
80 enum drm_dp_phy dp_phy) in intel_dp_read_lttpr_phy_caps() argument
490 lt_dbg(intel_dp, dp_phy, in intel_dp_get_adjust_train()
496 lt_dbg(intel_dp, dp_phy, in intel_dp_get_adjust_train()
522 enum drm_dp_phy dp_phy, in intel_dp_set_link_train() argument
597 enum drm_dp_phy dp_phy) in intel_dp_set_signal_levels() argument
602 lt_dbg(intel_dp, dp_phy, in intel_dp_set_signal_levels()
608 lt_dbg(intel_dp, dp_phy, in intel_dp_set_signal_levels()
853 lt_dbg(intel_dp, dp_phy, in intel_dp_dump_link_status()
1155 enum drm_dp_phy dp_phy) in intel_dp_link_train_phy() argument
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| A D | intel_dp_link_training.h | 28 enum drm_dp_phy dp_phy,
32 enum drm_dp_phy dp_phy,
36 enum drm_dp_phy dp_phy);
44 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
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| /drivers/phy/mediatek/ |
| A D | phy-mtk-dp.c | 87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init() local
111 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_configure() local
134 regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); in mtk_dp_phy_configure()
145 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_reset() local
147 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
150 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
166 struct mtk_dp_phy *dp_phy; in mtk_dp_phy_probe() local
175 dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL); in mtk_dp_phy_probe()
176 if (!dp_phy) in mtk_dp_phy_probe()
179 dp_phy->regs = regs; in mtk_dp_phy_probe()
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| /drivers/gpu/drm/msm/dp/ |
| A D | dp_ctrl.c | 1311 enum drm_dp_phy dp_phy) in msm_dp_ctrl_update_phy_vx_px() argument
1354 if (dp_phy == DP_PHY_DPRX) in msm_dp_ctrl_update_phy_vx_px()
1367 u8 pattern, enum drm_dp_phy dp_phy) in msm_dp_ctrl_train_pattern_set() argument
1380 if (dp_phy == DP_PHY_DPRX) in msm_dp_ctrl_train_pattern_set()
1414 int *training_step, enum drm_dp_phy dp_phy) in msm_dp_ctrl_link_train_1() argument
1422 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_1()
1432 DP_LINK_SCRAMBLING_DISABLE, dp_phy); in msm_dp_ctrl_link_train_1()
1518 enum drm_dp_phy dp_phy) in msm_dp_ctrl_clear_training_pattern() argument
1525 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_clear_training_pattern()
1540 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_2()
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| /drivers/gpu/drm/display/ |
| A D | drm_dp_helper.c | 288 enum drm_dp_phy dp_phy, bool uhbr, bool cr) in __read_delay() argument
294 if (dp_phy == DP_PHY_DPRX) { in __read_delay()
343 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_clock_recovery_delay() argument
350 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_channel_eq_delay() argument
433 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) || in drm_dp_phy_name()
434 WARN_ON(!phy_names[dp_phy])) in drm_dp_phy_name()
437 return phy_names[dp_phy]; in drm_dp_phy_name()
822 enum drm_dp_phy dp_phy, in drm_dp_dpcd_read_phy_link_status() argument
827 if (dp_phy == DP_PHY_DPRX) in drm_dp_dpcd_read_phy_link_status()
2654 if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT)) in drm_dp_dump_lttpr_desc()
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| /drivers/phy/qualcomm/ |
| A D | phy-qcom-qmp-combo.c | 1852 struct phy *dp_phy; member
3973 return qmp->dp_phy; in qmp_combo_phy_xlate()
4060 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); in qmp_combo_probe()
4061 if (IS_ERR(qmp->dp_phy)) { in qmp_combo_probe()
4062 ret = PTR_ERR(qmp->dp_phy); in qmp_combo_probe()
4067 phy_set_drvdata(qmp->dp_phy, qmp); in qmp_combo_probe()
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