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Searched refs:dpcd (Results 1 – 25 of 53) sorted by relevance

123

/drivers/gpu/drm/display/
A Ddrm_dp_helper.c329 rd_interval = dpcd[offset]; in __read_delay()
1239 if (dpcd[DP_DPCD_REV] == 0) in drm_dp_read_dpcd_caps()
1275 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) in drm_dp_read_downstream_info()
1310 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_dotclock()
1340 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_tmds_clock()
1405 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_min_tmds_clock()
1448 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_bpc()
1503 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_420_passthrough()
1534 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_444_to_420_conversion()
1566 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_rgb_to_ycbcr_conversion()
[all …]
/drivers/gpu/drm/nouveau/
A Dnouveau_dp.c69 u8 *dpcd = outp->dp.dpcd; in nouveau_dp_probe_dpcd() local
78 !drm_dp_read_dpcd_caps(aux, dpcd) && in nouveau_dp_probe_dpcd()
86 ret = drm_dp_read_dpcd_caps(aux, dpcd); in nouveau_dp_probe_dpcd()
121 outp->dp.rate[j].dpcd = i; in nouveau_dp_probe_dpcd()
130 u32 max_rate = dpcd[DP_MAX_LINK_RATE] * 27000; in nouveau_dp_probe_dpcd()
143 outp->dp.rate[outp->dp.rate_nr].dpcd = -1; in nouveau_dp_probe_dpcd()
189 ret = drm_dp_read_downstream_info(aux, dpcd, in nouveau_dp_probe_dpcd()
212 u8 *dpcd = nv_encoder->dp.dpcd; in nouveau_dp_detect() local
327 if ( (outp->dp.dpcd[DP_MAX_LANE_COUNT] & 0x20) && in nouveau_dp_train_link()
328 !(outp->dp.dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED)) in nouveau_dp_train_link()
[all …]
/drivers/gpu/drm/amd/amdgpu/
A Datombios_dp.c253 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_config()
260 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { in amdgpu_atombios_dp_ds_ports()
359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
362 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
369 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd()
481 if (dig_connector->dpcd[0] >= 0x11) { in amdgpu_atombios_dp_set_rx_power_state()
495 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
549 if (dp_info->dpcd[3] & 0x1) in amdgpu_atombios_dp_link_train_init()
561 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in amdgpu_atombios_dp_link_train_init()
[all …]
/drivers/gpu/drm/radeon/
A Datombios_dp.c302 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
308 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
309 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
391 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
394 dig_connector->dpcd); in radeon_dp_getdpcd()
401 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
524 if (dig_connector->dpcd[0] >= 0x11) { in radeon_dp_set_rx_power_state()
540 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
605 if (dp_info->dpcd[3] & 0x1) in radeon_dp_link_train_init()
617 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in radeon_dp_link_train_init()
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/drivers/gpu/drm/bridge/analogix/
A Danalogix-anx6345.c63 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
99 u8 dp_bw, dpcd[2]; in anx6345_dp_link_training() local
134 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); in anx6345_dp_link_training()
173 if (drm_dp_enhanced_frame_cap(anx6345->dpcd)) in anx6345_dp_link_training()
184 dpcd[0] = dp_bw; in anx6345_dp_link_training()
186 SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]); in anx6345_dp_link_training()
190 dpcd[1] = drm_dp_max_lane_count(anx6345->dpcd); in anx6345_dp_link_training()
193 SP_DP_LANE_COUNT_SET_REG, dpcd[1]); in anx6345_dp_link_training()
197 if (drm_dp_enhanced_frame_cap(anx6345->dpcd)) in anx6345_dp_link_training()
198 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; in anx6345_dp_link_training()
[all …]
A Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
606 u8 dp_bw, dpcd[2]; in anx78xx_dp_link_training() local
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
667 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { in anx78xx_dp_link_training()
686 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
699 anx78xx->dpcd[DP_MAX_LINK_RATE]); in anx78xx_dp_link_training()
703 dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd); in anx78xx_dp_link_training()
705 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
706 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; in anx78xx_dp_link_training()
708 err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd, in anx78xx_dp_link_training()
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
A Ddp.c242 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 && in nvkm_dp_train_eq()
243 lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED) in nvkm_dp_train_eq()
246 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 && in nvkm_dp_train_eq()
247 lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
318 .pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED, in nvkm_dp_train_link()
327 sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0; in nvkm_dp_train_link()
338 if (outp->dp.rate[rate].dpcd >= 0) { in nvkm_dp_train_link()
344 sink[0] |= outp->dp.rate[rate].dpcd; in nvkm_dp_train_link()
382 outp->dp.dpcd[DPCD_RC03] &= ~DPCD_RC03_TPS4_SUPPORTED; in nvkm_dp_train_links()
384 outp->dp.dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
[all …]
A Doutp.h48 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
51 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ member
A Duoutp.c90 outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP, in nvkm_uoutp_mthd_dp_sst()
118 memcpy(outp->dp.dpcd, args->v0.dpcd, sizeof(outp->dp.dpcd)); in nvkm_uoutp_mthd_dp_train()
140 outp->dp.rate[i].dpcd = args->v0.rate[i].dpcd; in nvkm_uoutp_mthd_dp_rates()
/drivers/gpu/drm/tegra/
A Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe() local
178 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); in drm_dp_link_probe()
182 link->revision = dpcd[DP_DPCD_REV]; in drm_dp_link_probe()
183 link->max_rate = drm_dp_max_link_rate(dpcd); in drm_dp_link_probe()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
186 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); in drm_dp_link_probe()
187 link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); in drm_dp_link_probe()
188 link->caps.fast_training = drm_dp_fast_training_cap(dpcd); in drm_dp_link_probe()
189 link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); in drm_dp_link_probe()
191 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { in drm_dp_link_probe()
[all …]
/drivers/gpu/drm/msm/dp/
A Ddp_panel.c76 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { in msm_dp_panel_read_psr_cap()
94 u8 *dpcd, major, minor; in msm_dp_panel_read_dpcd() local
97 dpcd = msm_dp_panel->dpcd; in msm_dp_panel_read_dpcd()
98 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); in msm_dp_panel_read_dpcd()
102 msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); in msm_dp_panel_read_dpcd()
104 link_info->revision = dpcd[DP_DPCD_REV]; in msm_dp_panel_read_dpcd()
108 link_info->rate = drm_dp_max_link_rate(dpcd); in msm_dp_panel_read_dpcd()
109 link_info->num_lanes = drm_dp_max_lane_count(dpcd); in msm_dp_panel_read_dpcd()
133 if (drm_dp_enhanced_frame_cap(dpcd)) in msm_dp_panel_read_dpcd()
194 if (drm_dp_is_branch(msm_dp_panel->dpcd)) { in msm_dp_panel_read_sink_caps()
[all …]
A Ddp_ctrl.c386 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_config_ctrl() local
395 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) in msm_dp_ctrl_config_ctrl()
407 if (drm_dp_enhanced_frame_cap(dpcd)) in msm_dp_ctrl_config_ctrl()
1422 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_1()
1525 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_clear_training_pattern()
1540 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_2()
1546 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1612 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_link_train() local
1625 if (drm_dp_max_downspread(dpcd)) in msm_dp_ctrl_link_train()
1631 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { in msm_dp_ctrl_link_train()
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/drivers/gpu/drm/i915/display/
A Dintel_dp_link_training.c79 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in intel_dp_read_lttpr_phy_caps()
95 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_lttpr_common_caps()
151 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) in intel_dp_init_lttpr_phys()
227 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) in intel_dp_read_dprx_caps()
262 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_init_lttpr_and_dprx_caps() local
263 int err = intel_dp_read_dprx_caps(intel_dp, dpcd); in intel_dp_init_lttpr_and_dprx_caps()
268 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); in intel_dp_init_lttpr_and_dprx_caps()
875 intel_dp->dpcd, dp_phy, in intel_dp_link_training_clock_recovery()
976 drm_dp_tps4_supported(intel_dp->dpcd); in intel_dp_training_pattern()
994 drm_dp_tps3_supported(intel_dp->dpcd); in intel_dp_training_pattern()
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A Dintel_dp.c1118 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_rgb()
1135 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_ycbcr444()
3371 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
3735 if (!drm_dp_is_branch(intel_dp->dpcd)) in intel_dp_get_pcon_dsc_cap()
4347 drm_dp_is_branch(intel_dp->dpcd)); in intel_edp_init_dpcd()
4400 intel_dp->dpcd, in intel_dp_has_sink_count()
5519 u8 *dpcd = intel_dp->dpcd; in intel_dp_detect_dpcd() local
5533 if (!drm_dp_is_branch(dpcd)) in intel_dp_detect_dpcd()
5957 intel_dp->dpcd, in intel_dp_detect()
6009 intel_dp->dpcd, in intel_dp_get_modes()
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A Dintel_alpm.c38 u8 dpcd; in intel_alpm_init() local
40 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0) in intel_alpm_init()
43 intel_dp->alpm_dpcd = dpcd; in intel_alpm_init()
/drivers/gpu/drm/gma500/
A Dcdv_intel_dp.c263 uint8_t dpcd[4]; member
326 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in cdv_intel_dp_max_lane_count()
1110 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in cdv_intel_dp_sink_dpms()
1670 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) in cdv_dp_detect()
1672 if (intel_dp->dpcd[DP_DPCD_REV] != 0) in cdv_dp_detect()
1677 intel_dp->dpcd[0], intel_dp->dpcd[1], in cdv_dp_detect()
1678 intel_dp->dpcd[2], intel_dp->dpcd[3]); in cdv_dp_detect()
2067 intel_dp->dpcd, in cdv_intel_dp_init()
2068 sizeof(intel_dp->dpcd)); in cdv_intel_dp_init()
2078 intel_dp->dpcd[0], intel_dp->dpcd[1], in cdv_intel_dp_init()
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/drivers/gpu/drm/i915/gvt/
A Ddisplay.c534 kfree(port->dpcd); in clean_virtual_dp_monitor()
535 port->dpcd = NULL; in clean_virtual_dp_monitor()
567 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); in setup_virtual_dp_monitor()
568 if (!port->dpcd) { in setup_virtual_dp_monitor()
577 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); in setup_virtual_dp_monitor()
578 port->dpcd->data_valid = true; in setup_virtual_dp_monitor()
579 port->dpcd->data[DP_SINK_COUNT] = 0x1; in setup_virtual_dp_monitor()
A Dhandlers.c1146 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CR_DONE | in dp_aux_ch_ctl_link_training()
1165 dpcd->data[DP_LANE_ALIGN_STATUS_UPDATED] |= in dp_aux_ch_ctl_link_training()
1187 struct intel_vgpu_dpcd_data *dpcd = NULL; in dp_aux_ch_ctl_mmio_write() local
1218 dpcd = port->dpcd; in dp_aux_ch_ctl_mmio_write()
1267 if (dpcd && dpcd->data_valid) { in dp_aux_ch_ctl_mmio_write()
1271 dpcd->data[p] = buf[t]; in dp_aux_ch_ctl_mmio_write()
1274 dp_aux_ch_ctl_link_training(dpcd, in dp_aux_ch_ctl_mmio_write()
1282 dpcd && dpcd->data_valid); in dp_aux_ch_ctl_mmio_write()
1325 if (dpcd && dpcd->data_valid) { in dp_aux_ch_ctl_mmio_write()
1329 t = dpcd->data[addr + i - 1]; in dp_aux_ch_ctl_mmio_write()
[all …]
/drivers/gpu/drm/bridge/
A Dite-it6505.c452 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
664 num, dpcd); in it6505_get_dpcd()
1643 if (it6505->dpcd[0] == 0) { in it6505_parse_link_capabilities()
1650 link->revision = it6505->dpcd[0]; in it6505_parse_link_capabilities()
2477 memset(it6505->dpcd, 0, sizeof(it6505->dpcd)); in it6505_process_hpd_irq()
2539 if (it6505->dpcd[0] == 0) { in it6505_irq_hpd()
2541 ARRAY_SIZE(it6505->dpcd)); in it6505_irq_hpd()
2570 memset(it6505->dpcd, 0, sizeof(it6505->dpcd)); in it6505_irq_hpd()
2893 memset(it6505->dpcd, 0, sizeof(it6505->dpcd)); in it6505_detect()
2953 memset(it6505->dpcd, 0, sizeof(it6505->dpcd)); in it6505_extcon_work()
[all …]
/drivers/gpu/drm/nouveau/nvif/
A Doutp.c113 nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, in nvif_outp_dp_train()
126 memcpy(args.dpcd, dpcd, sizeof(args.dpcd)); in nvif_outp_dp_train()
148 args.rate[i].dpcd = rate->dpcd; in nvif_outp_dp_rates()
/drivers/gpu/drm/hisilicon/hibmc/dp/
A Ddp_link.c213 drm_dp_link_train_clock_recovery_delay(dp->aux, dp->dpcd); in hibmc_dp_link_training_cr()
266 drm_dp_link_train_channel_eq_delay(dp->aux, dp->dpcd); in hibmc_dp_link_training_channel_eq()
333 ret = drm_dp_read_dpcd_caps(dp->aux, dp->dpcd); in hibmc_dp_link_training()
337 dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE]; in hibmc_dp_link_training()
/drivers/gpu/drm/nouveau/include/nvif/
A Doutp.h102 int dpcd; /* -1 for non-indexed rates */ member
107 int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
A Dif0012.h228 __s8 dpcd; member
243 __u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/drivers/gpu/drm/xlnx/
A Dzynqmp_dp.c406 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
835 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && in zynqmp_dp_link_train_ce()
836 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) in zynqmp_dp_link_train_ce()
852 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_ce()
950 drm_dp_enhanced_frame_cap(dp->dpcd), in zynqmp_dp_train()
951 dp->dpcd[DP_MAX_DOWNSPREAD] & in zynqmp_dp_train()
1700 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, in __zynqmp_dp_bridge_detect()
1701 sizeof(dp->dpcd)); in __zynqmp_dp_bridge_detect()
1708 drm_dp_max_link_rate(dp->dpcd), in __zynqmp_dp_bridge_detect()
1711 drm_dp_max_lane_count(dp->dpcd), in __zynqmp_dp_bridge_detect()
[all …]
/drivers/gpu/drm/bridge/cadence/
A Dcdns-mhdp8546-core.c1331 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps()
1339 mhdp->sink.ssc = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1344 if (drm_dp_tps3_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1346 if (drm_dp_tps4_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1350 mhdp->sink.fast_link = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1356 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up() local
1378 mhdp->link.revision = dpcd[0]; in cdns_mhdp_link_up()
1379 mhdp->link.rate = drm_dp_bw_code_to_link_rate(dpcd[1]); in cdns_mhdp_link_up()
1380 mhdp->link.num_lanes = dpcd[2] & DP_MAX_LANE_COUNT_MASK; in cdns_mhdp_link_up()
1382 if (dpcd[2] & DP_ENHANCED_FRAME_CAP) in cdns_mhdp_link_up()
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