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Searched refs:dpll (Results 1 – 25 of 64) sorted by relevance

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/drivers/dpll/
A Ddpll_netlink.c867 dpll = ref->dpll; in dpll_pin_freq_set()
879 dpll = ref->dpll; in dpll_pin_freq_set()
898 dpll = ref->dpll; in dpll_pin_freq_set()
929 dpll = ref->dpll; in dpll_pin_esync_set()
951 dpll = ref->dpll; in dpll_pin_esync_set()
974 dpll = ref->dpll; in dpll_pin_esync_set()
1015 dpll = ref->dpll; in dpll_pin_ref_sync_state_set()
1028 dpll = ref->dpll; in dpll_pin_ref_sync_state_set()
1050 dpll = ref->dpll; in dpll_pin_ref_sync_state_set()
1236 dpll = ref->dpll; in dpll_pin_phase_adj_set()
[all …]
A Ddpll_core.c164 if (ref->dpll != dpll) in dpll_xa_ref_dpll_add()
179 ref->dpll = dpll; in dpll_xa_ref_dpll_add()
216 if (ref->dpll != dpll) in dpll_xa_ref_dpll_del()
248 dpll = kzalloc(sizeof(*dpll), GFP_KERNEL); in dpll_device_alloc()
249 if (!dpll) in dpll_device_alloc()
256 ret = xa_alloc_cyclic(&dpll_device_xa, &dpll->id, dpll, xa_limit_32b, in dpll_device_alloc()
259 kfree(dpll); in dpll_device_alloc()
264 return dpll; in dpll_device_alloc()
292 ret = dpll; in dpll_device_get()
322 kfree(dpll); in dpll_device_put()
[all …]
A DMakefile6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
A Ddpll_core.h74 struct dpll_device *dpll; member
81 void *dpll_priv(struct dpll_device *dpll);
82 void *dpll_pin_on_dpll_priv(struct dpll_device *dpll, struct dpll_pin *pin);
85 const struct dpll_device_ops *dpll_device_ops(struct dpll_device *dpll);
A Ddpll_netlink.h7 int dpll_device_create_ntf(struct dpll_device *dpll);
9 int dpll_device_delete_ntf(struct dpll_device *dpll);
A DKconfig11 source "drivers/dpll/zl3073x/Kconfig"
/drivers/gpu/drm/i915/display/
A Dintel_dpll.c333 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
428 u32 dpll = hw_state->dpll; in i9xx_crtc_clock_get() local
987 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
989 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
994 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
1007 u32 dpll; in i9xx_dpll() local
1252 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1905 const struct dpll *clock = &crtc_state->dpll; in vlv_prepare_pll()
2026 const struct dpll *clock = &crtc_state->dpll; in chv_prepare_pll()
2202 const struct dpll *dpll) in vlv_force_pll_on() argument
[all …]
A Dintel_dpll.h12 struct dpll;
24 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
25 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
32 const struct dpll *dpll);
42 struct dpll *best_clock);
43 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
A Dintel_dpll_mgr.c543 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
655 hw_state->dpll, in ibx_dump_hw_state()
667 return a->dpll == b->dpll && in ibx_compare_hw_state()
2257 struct dpll *clk_div) in bxt_ddi_hdmi_pll_dividers()
2367 struct dpll clock; in bxt_ddi_pll_get_freq()
2384 struct dpll clk_div = {}; in bxt_ddi_dp_set_dpll_hw_state()
2395 struct dpll clk_div = {}; in bxt_ddi_hdmi_set_dpll_hw_state()
4360 display->dpll.num_dpll = i; in intel_dpll_init()
4535 if (display->dpll.mgr && display->dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4589 if (display->dpll.mgr) { in intel_dpll_dump_hw_state()
[all …]
A Dg4x_dp.h21 const struct dpll *vlv_get_dpll(struct intel_display *display);
28 static inline const struct dpll *vlv_get_dpll(struct intel_display *display) in vlv_get_dpll()
A Dintel_dpll_mgr.h34 for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \
35 ((__pll) = &(__display)->dpll.dplls[(__i)]) ; (__i)++)
184 u32 dpll; member
A Dintel_pch_refclk.c467 display->dpll.pch_ssc_use = 0; in lpt_init_pch_refclk()
471 display->dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL); in lpt_init_pch_refclk()
476 display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1); in lpt_init_pch_refclk()
481 display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2); in lpt_init_pch_refclk()
484 if (display->dpll.pch_ssc_use) in lpt_init_pch_refclk()
/drivers/gpu/drm/gma500/
A Dpsb_intel_display.c168 dpll |= in psb_intel_crtc_mode_set()
192 dpll |= 3; in psb_intel_crtc_mode_set()
220 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
255 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
256 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
261 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
310 u32 dpll; in psb_intel_crtc_clock_get() local
317 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
325 dpll = p->dpll; in psb_intel_crtc_clock_get()
342 ffs((dpll & in psb_intel_crtc_clock_get()
[all …]
A Doaktrail_crtc.c251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
527 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
530 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
533 dpll |= DPLLA_MODE_LVDS; in oaktrail_crtc_mode_set()
541 dpll |= DPLL_DVO_HIGH_SPEED; in oaktrail_crtc_mode_set()
542 dpll |= in oaktrail_crtc_mode_set()
554 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
556 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set()
559 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
568 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
[all …]
A Dcdv_intel_display.c665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
758 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
842 u32 dpll; in cdv_intel_crtc_clock_get() local
849 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
857 dpll = p->dpll; in cdv_intel_crtc_clock_get()
873 ffs((dpll & in cdv_intel_crtc_clock_get()
[all …]
A Dgma_display.c223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
314 REG_READ(map->dpll); in gma_crtc_dpms()
595 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save()
634 REG_WRITE(map->dpll, in gma_crtc_restore()
636 REG_READ(map->dpll); in gma_crtc_restore()
[all …]
A Doaktrail_hdmi.c285 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
295 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
296 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
297 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
311 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
312 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
313 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
317 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
A Doaktrail_device.c144 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers()
261 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers()
402 .dpll = MRST_DPLL_A,
426 .dpll = DPLL_B,
/drivers/net/ethernet/intel/ice/
A Dice_dpll.c1754 dpll, dpll_priv, in ice_dpll_sw_phase_adjust_get()
3163 pf->dplls.eec.dpll, pf->dplls.pps.dpll); in ice_dpll_init_pins()
3172 pf->dplls.eec.dpll, in ice_dpll_init_pins()
3173 pf->dplls.pps.dpll); in ice_dpll_init_pins()
3182 pf->dplls.eec.dpll, in ice_dpll_init_pins()
3191 pf->dplls.eec.dpll, in ice_dpll_init_pins()
3218 pf->dplls.pps.dpll, pf->dplls.eec.dpll); in ice_dpll_init_pins()
3223 pf->dplls.pps.dpll, pf->dplls.eec.dpll); in ice_dpll_init_pins()
3250 dpll_device_put(d->dpll); in ice_dpll_deinit_dpll()
3275 if (IS_ERR(d->dpll)) { in ice_dpll_init_dpll()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/
A Ddpll.c11 struct dpll_device *dpll; member
257 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
268 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
286 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
352 dpll_device_change_ntf(mdpll->dpll); in mlx5_dpll_periodic_work()
442 if (IS_ERR(mdpll->dpll)) { in mlx5_dpll_probe()
443 err = PTR_ERR(mdpll->dpll); in mlx5_dpll_probe()
479 dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, in mlx5_dpll_probe()
486 dpll_device_put(mdpll->dpll); in mlx5_dpll_probe()
500 dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, in mlx5_dpll_remove()
[all …]
/drivers/dpll/zl3073x/
A Ddpll.c44 struct zl3073x_dpll *dpll; member
158 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_get() argument
224 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_set() argument
518 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_phase_offset_get() argument
594 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_phase_adjust_get() argument
634 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_phase_adjust_set() argument
823 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_state_on_dpll_get() argument
836 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_state_on_dpll_set() argument
946 const struct dpll_device *dpll, in zl3073x_dpll_output_pin_esync_get() argument
1061 const struct dpll_device *dpll, in zl3073x_dpll_output_pin_esync_set() argument
[all …]
A Dcore.h61 u8 dpll; member
224 return zldev->synth[index].dpll; in zl3073x_synth_dpll_get()
/drivers/ata/
A Dpata_hpt3x2n.c312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
A Dpata_hpt37x.c948 int dpll, adjust; in hpt37x_init_one() local
951 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
953 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
981 if (dpll == 3) in hpt37x_init_one()
987 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/drivers/gpu/drm/renesas/rcar-du/
A Drcar_du_crtc.c83 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
147 dpll->n = n; in rcar_du_dpll_divider()
148 dpll->m = m; in rcar_du_dpll_divider()
149 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
150 dpll->output = output; in rcar_du_dpll_divider()
162 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
217 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local
227 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing()
230 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing()
231 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) in rcar_du_crtc_set_display_timing()

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