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Searched refs:dpll_md (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/gma500/
A Dcdv_intel_crt.c97 u32 adpa, dpll_md; in cdv_intel_crt_mode_set() local
112 dpll_md = REG_READ(dpll_md_reg); in cdv_intel_crt_mode_set()
114 dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); in cdv_intel_crt_mode_set()
A Dcdv_device.c504 .dpll_md = DPLL_A_MD,
529 .dpll_md = DPLL_B_MD,
A Dpsb_drv.h228 u32 dpll_md; member
262 u32 dpll_md; member
A Dcdv_intel_display.c780 …REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_U… in cdv_intel_crtc_mode_set()
/drivers/gpu/drm/i915/display/
A Dintel_dpll.c406 hw_state->dpll_md = tmp; in i9xx_dpll_get_hw_state()
1089 hw_state->dpll_md = i965_dpll_md(crtc_state); in i9xx_compute_dpll()
1444 hw_state->dpll_md = i965_dpll_md(crtc_state); in vlv_compute_dpll()
1470 hw_state->dpll_md = i965_dpll_md(crtc_state); in chv_compute_dpll()
1854 hw_state->dpll_md); in i9xx_enable_pll()
2018 intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md); in vlv_enable_pll()
2173 hw_state->dpll_md); in chv_enable_pll()
2175 display->state.chv_dpll_md[pipe] = hw_state->dpll_md; in chv_enable_pll()
2186 hw_state->dpll_md); in chv_enable_pll()
A Dintel_dpll_mgr.h185 u32 dpll_md; member
A Dintel_dpll_mgr.c656 hw_state->dpll_md, in ibx_dump_hw_state()
668 a->dpll_md == b->dpll_md && in ibx_compare_hw_state()
A Dintel_display.c3081 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; in i9xx_get_pipe_config()

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