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Searched refs:dpm_level (Results 1 – 25 of 30) sorted by relevance

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/drivers/accel/amdxdna/
A Daie2_smu.c57 int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) in npu1_set_dpm() argument
63 ndev->priv->dpm_clk_tbl[dpm_level].npuclk, &freq); in npu1_set_dpm()
66 ndev->priv->dpm_clk_tbl[dpm_level].npuclk, ret); in npu1_set_dpm()
72 ndev->priv->dpm_clk_tbl[dpm_level].hclk, &freq); in npu1_set_dpm()
75 ndev->priv->dpm_clk_tbl[dpm_level].hclk, ret); in npu1_set_dpm()
79 ndev->dpm_level = dpm_level; in npu1_set_dpm()
87 int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) in npu4_set_dpm() argument
94 dpm_level, ret); in npu4_set_dpm()
101 dpm_level, ret); in npu4_set_dpm()
106 ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk; in npu4_set_dpm()
[all …]
A Daie2_pm.c35 ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->dpm_level); in aie2_pm_init()
67 u32 clk_gating, dpm_level; in aie2_pm_set_mode() local
83 dpm_level = ndev->max_dpm_level; in aie2_pm_set_mode()
87 dpm_level = ndev->max_dpm_level; in aie2_pm_set_mode()
91 dpm_level = ndev->dft_dpm_level; in aie2_pm_set_mode()
97 ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level); in aie2_pm_set_mode()
A Daie2_solver.c29 u32 dpm_level; member
112 static int set_dpm_level(struct solver_state *xrs, struct alloc_requests *req, u32 *dpm_level) in set_dpm_level() argument
136 if (node->dpm_level > level) in set_dpm_level()
137 level = node->dpm_level; in set_dpm_level()
141 *dpm_level = level; in set_dpm_level()
304 u32 dpm_level; in xrs_allocate_resource() local
329 ret = set_dpm_level(xrs, req, &dpm_level); in xrs_allocate_resource()
333 snode->dpm_level = dpm_level; in xrs_allocate_resource()
A Daie2_pci.h179 u32 dpm_level; member
204 int (*set_dpm)(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
241 int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
242 int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
A Daie2_pci.c301 static int aie2_xrs_set_dft_dpm_level(struct drm_device *ddev, u32 dpm_level) in aie2_xrs_set_dft_dpm_level() argument
309 ndev->dft_dpm_level = dpm_level; in aie2_xrs_set_dft_dpm_level()
310 if (ndev->pw_mode != POWER_MODE_DEFAULT || ndev->dpm_level == dpm_level) in aie2_xrs_set_dft_dpm_level()
313 return ndev->priv->hw_ops.set_dpm(ndev, dpm_level); in aie2_xrs_set_dft_dpm_level()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_0_ppt.c632 uint32_t dpm_level, in smu_v14_0_1_get_dpm_freq_by_index() argument
644 *freq = clk_table->SocClocks[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
649 *freq = clk_table->VClocks0[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
654 *freq = clk_table->DClocks0[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
659 *freq = clk_table->VClocks1[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
664 *freq = clk_table->DClocks1[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
686 uint32_t dpm_level, in smu_v14_0_0_get_dpm_freq_by_index() argument
698 *freq = clk_table->SocClocks[dpm_level]; in smu_v14_0_0_get_dpm_freq_by_index()
703 *freq = clk_table->VClocks[dpm_level]; in smu_v14_0_0_get_dpm_freq_by_index()
708 *freq = clk_table->DClocks[dpm_level]; in smu_v14_0_0_get_dpm_freq_by_index()
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/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_5_ppt.c656 uint32_t dpm_level, in smu_v13_0_5_get_dpm_freq_by_index() argument
666 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
668 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
671 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
673 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
676 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
678 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
682 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
684 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in smu_v13_0_5_get_dpm_freq_by_index()
687 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
[all …]
A Dsmu_v13_0_4_ppt.c426 uint32_t dpm_level, in smu_v13_0_4_get_dpm_freq_by_index() argument
436 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
438 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
441 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
443 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
446 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
448 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
452 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
454 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in smu_v13_0_4_get_dpm_freq_by_index()
457 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
[all …]
A Dyellow_carp_ppt.c790 uint32_t dpm_level, in yellow_carp_get_dpm_freq_by_index() argument
800 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
802 *freq = clk_table->SocClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
805 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
807 *freq = clk_table->VClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
810 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
812 *freq = clk_table->DClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
816 if (dpm_level >= clk_table->NumDfPstatesEnabled) in yellow_carp_get_dpm_freq_by_index()
818 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in yellow_carp_get_dpm_freq_by_index()
821 if (dpm_level >= clk_table->NumDfPstatesEnabled) in yellow_carp_get_dpm_freq_by_index()
[all …]
A Daldebaran_ppt.c1331 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && in aldebaran_set_performance_level()
1376 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in aldebaran_set_soft_freq_limited_range()
1377 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) in aldebaran_set_soft_freq_limited_range()
1380 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { in aldebaran_set_soft_freq_limited_range()
1401 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { in aldebaran_set_soft_freq_limited_range()
1442 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in aldebaran_usr_edit_dpm_table()
1443 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) in aldebaran_usr_edit_dpm_table()
A Dsmu_v13_0_6_ppt.c1971 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && in smu_v13_0_6_set_performance_level()
2030 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) && in smu_v13_0_6_set_soft_freq_limited_range()
2031 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) in smu_v13_0_6_set_soft_freq_limited_range()
2034 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { in smu_v13_0_6_set_soft_freq_limited_range()
2071 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { in smu_v13_0_6_set_soft_freq_limited_range()
2116 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) && in smu_v13_0_6_usr_edit_dpm_table()
2117 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) in smu_v13_0_6_usr_edit_dpm_table()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c203 uint32_t dpm_level, uint32_t *freq) in renoir_get_dpm_clk_limited() argument
212 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
218 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
220 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
223 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
228 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
230 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
233 if (dpm_level >= NUM_VCN_DPM_LEVELS) in renoir_get_dpm_clk_limited()
235 *freq = clk_table->VClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
238 if (dpm_level >= NUM_VCN_DPM_LEVELS) in renoir_get_dpm_clk_limited()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr_smu_msg.c261 … dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level) in dcn30_smu_get_dpm_freq_by_index() argument
266 uint32_t param = (clk << 16) | dpm_level; in dcn30_smu_get_dpm_freq_by_index()
268 smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level); in dcn30_smu_get_dpm_freq_by_index()
A Ddcn30_clk_mgr_smu_msg.h43 …dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu_helper.c356 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
367 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
368 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
369 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
380 if (dpm_table->dpm_level[i - 1].enabled) in phm_get_dpm_level_enable_mask_value()
451 if (value == dpm_table->dpm_level[i].value) { in phm_find_boot_level()
A Dpp_psm.c295 hwmgr->dpm_level = hwmgr->request_dpm_level; in psm_adjust_power_state_dynamic()
297 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in psm_adjust_power_state_dynamic()
A Dvega12_hwmgr.c2384 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { in vega12_apply_clocks_adjust_rules()
2389 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2408 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { in vega12_apply_clocks_adjust_rules()
2413 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2452 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2471 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2490 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2509 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
A Dvega20_hwmgr.c3766 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { in vega20_apply_clocks_adjust_rules()
3771 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3790 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { in vega20_apply_clocks_adjust_rules()
3795 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3850 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3869 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3888 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3907 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
A Dhwmgr.c87 hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; in hwmgr_early_init()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c520 uint32_t dpm_level, uint32_t *freq) in vangogh_get_dpm_clk_limited() argument
529 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
531 *freq = clk_table->SocClocks[dpm_level]; in vangogh_get_dpm_clk_limited()
534 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
536 *freq = clk_table->VcnClocks[dpm_level].vclk; in vangogh_get_dpm_clk_limited()
539 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
541 *freq = clk_table->VcnClocks[dpm_level].dclk; in vangogh_get_dpm_clk_limited()
545 if (dpm_level >= clk_table->NumDfPstatesEnabled) in vangogh_get_dpm_clk_limited()
547 *freq = clk_table->DfPstateTable[dpm_level].memclk; in vangogh_get_dpm_clk_limited()
551 if (dpm_level >= clk_table->NumDfPstatesEnabled) in vangogh_get_dpm_clk_limited()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c519 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { in smu_restore_dpm_user_profile()
944 smu->smu_dpm.dpm_level, in smu_late_init()
1344 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; in smu_sw_init()
2239 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { in smu_resume()
2293 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { in smu_enable_umd_pstate()
2296 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; in smu_enable_umd_pstate()
2385 if (smu_dpm_ctx->dpm_level != level) { in smu_adjust_power_state_dynamic()
2398 smu_dpm_ctx->dpm_level = level; in smu_adjust_power_state_dynamic()
2401 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && in smu_adjust_power_state_dynamic()
2444 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); in smu_handle_dpm_task()
[all …]
/drivers/gpu/drm/amd/pm/powerplay/
A Damd_powerplay.c354 if (!(hwmgr->dpm_level & profile_mode_mask)) { in pp_dpm_en_umd_pstate()
357 hwmgr->saved_dpm_level = hwmgr->dpm_level; in pp_dpm_en_umd_pstate()
378 if (level == hwmgr->dpm_level) in pp_dpm_force_performance_level()
396 return hwmgr->dpm_level; in pp_dpm_get_performance_level()
703 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_dpm_force_clock_level()
863 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_set_power_profile_mode()
952 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in pp_dpm_switch_power_profile()
/drivers/gpu/drm/amd/pm/powerplay/inc/
A Dhwmgr.h63 struct vi_dpm_level dpm_level[]; member
763 enum amd_dpm_forced_level dpm_level; member
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c1755 int dpm_level = 0; in dcn401_get_power_profile() local
1762 dpm_level++; in dcn401_get_power_profile()
1765 return dpm_level; in dcn401_get_power_profile()
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Damdgpu_smu.h390 enum amd_dpm_forced_level dpm_level; member

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