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Searched refs:dpm_levels (Results 1 – 25 of 32) sorted by relevance

12

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega12_hwmgr.c628 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
629 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
805 dpm_table->dpm_levels[min_level].value;
1126 if (table->dpm_levels[i].enabled) in vega12_find_lowest_dpm_level()
1132 table->dpm_levels[i].enabled = true; in vega12_find_lowest_dpm_level()
1147 if (table->dpm_levels[i].enabled) in vega12_find_highest_dpm_level()
1153 table->dpm_levels[i].enabled = true; in vega12_find_highest_dpm_level()
1872 dpm_table->dpm_levels[i].value * 1000; in vega12_get_sclks()
1933 dpm_table->dpm_levels[i].value * 1000; in vega12_get_dcefclocks()
1961 dpm_table->dpm_levels[i].value * 1000; in vega12_get_socclocks()
[all …]
A Dvega20_hwmgr.c586 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
587 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
1782 if (table->dpm_levels[i].enabled) in vega20_find_lowest_dpm_level()
1787 table->dpm_levels[i].enabled = true; in vega20_find_lowest_dpm_level()
1809 if (table->dpm_levels[i].enabled) in vega20_find_highest_dpm_level()
1814 table->dpm_levels[i].enabled = true; in vega20_find_highest_dpm_level()
2830 dpm_table->dpm_levels[i].value * 1000; in vega20_get_sclks()
2859 dpm_table->dpm_levels[i].value * 1000; in vega20_get_memclocks()
2883 dpm_table->dpm_levels[i].value * 1000; in vega20_get_dcefclocks()
2905 dpm_table->dpm_levels[i].value * 1000; in vega20_get_socclocks()
[all …]
A Dvega10_hwmgr.c1739 dpm_table->dpm_levels[i].value, in vega10_populate_all_graphic_levels()
1749 dpm_table->dpm_levels[j].value, in vega10_populate_all_graphic_levels()
1763 dpm_table->dpm_levels[i].value, in vega10_populate_all_graphic_levels()
1773 dpm_table->dpm_levels[j].value, in vega10_populate_all_graphic_levels()
1889 dpm_table->dpm_levels[i].value, in vega10_populate_all_memory_levels()
1900 dpm_table->dpm_levels[j].value, in vega10_populate_all_memory_levels()
2026 dpm_table->dpm_levels[i].value, in vega10_populate_smc_vce_levels()
5183 golden_sclk_table->dpm_levels in vega10_set_sclk_od()
5186 golden_sclk_table->dpm_levels in vega10_set_sclk_od()
5236 golden_mclk_table->dpm_levels in vega10_set_mclk_od()
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A Dsmu7_hwmgr.c4100 if (sclk == sclk_table->dpm_levels[i].value) in smu7_find_dpm_states_clocks_in_dpm_table()
4107 sclk_table->dpm_levels[i-1].value = sclk; in smu7_find_dpm_states_clocks_in_dpm_table()
4120 if (mclk == mclk_table->dpm_levels[i].value) in smu7_find_dpm_states_clocks_in_dpm_table()
4127 mclk_table->dpm_levels[i-1].value = mclk; in smu7_find_dpm_states_clocks_in_dpm_table()
4154 dpm_table->pcie_speed_table.dpm_levels in smu7_get_maximum_link_speed()
4309 dpm_table->dpm_levels[i].enabled = false; in smu7_trim_single_dpm_states()
4311 dpm_table->dpm_levels[i].enabled = true; in smu7_trim_single_dpm_states()
4991 i, sclk_table->dpm_levels[i].value / 100, in smu7_print_clock_levels()
5007 i, mclk_table->dpm_levels[i].value / 100, in smu7_print_clock_levels()
5427 mclk_table->dpm_levels[0].value; in smu7_get_max_high_clocks()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_7_ppt.c595 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
619 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
635 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
651 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
667 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
683 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
699 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
1257 single_dpm_table->dpm_levels[0].value); in smu_v13_0_7_print_clk_levels()
1261 single_dpm_table->dpm_levels[1].value); in smu_v13_0_7_print_clk_levels()
1264 single_dpm_table->dpm_levels[0].value, in smu_v13_0_7_print_clk_levels()
[all …]
A Daldebaran_ppt.c418 dpm_table->dpm_levels[0].enabled = true; in aldebaran_set_default_dpm_table()
419 dpm_table->min = dpm_table->dpm_levels[0].value; in aldebaran_set_default_dpm_table()
420 dpm_table->max = dpm_table->dpm_levels[0].value; in aldebaran_set_default_dpm_table()
429 dpm_table->dpm_levels[0].enabled = true; in aldebaran_set_default_dpm_table()
431 dpm_table->dpm_levels[1].enabled = true; in aldebaran_set_default_dpm_table()
432 dpm_table->min = dpm_table->dpm_levels[0].value; in aldebaran_set_default_dpm_table()
433 dpm_table->max = dpm_table->dpm_levels[1].value; in aldebaran_set_default_dpm_table()
437 dpm_table->dpm_levels[0].enabled = true; in aldebaran_set_default_dpm_table()
453 dpm_table->dpm_levels[0].enabled = true; in aldebaran_set_default_dpm_table()
469 dpm_table->dpm_levels[0].enabled = true; in aldebaran_set_default_dpm_table()
[all …]
A Dsmu_v13_0_0_ppt.c588 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
621 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
637 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
653 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
669 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
685 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
701 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
1268 single_dpm_table->dpm_levels[0].value); in smu_v13_0_0_print_clk_levels()
1272 single_dpm_table->dpm_levels[1].value); in smu_v13_0_0_print_clk_levels()
1275 single_dpm_table->dpm_levels[0].value, in smu_v13_0_0_print_clk_levels()
[all …]
A Dsmu_v13_0_6_ppt.c1037 dpm_table->dpm_levels[0].value = gfxclkmin; in smu_v13_0_6_set_default_dpm_table()
1038 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_6_set_default_dpm_table()
1039 dpm_table->dpm_levels[1].value = gfxclkmax; in smu_v13_0_6_set_default_dpm_table()
1040 dpm_table->dpm_levels[1].enabled = true; in smu_v13_0_6_set_default_dpm_table()
1041 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_6_set_default_dpm_table()
1042 dpm_table->max = dpm_table->dpm_levels[1].value; in smu_v13_0_6_set_default_dpm_table()
1046 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_6_set_default_dpm_table()
1047 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_6_set_default_dpm_table()
1062 dpm_table->dpm_levels[i].value = in smu_v13_0_6_set_default_dpm_table()
1064 dpm_table->dpm_levels[i].enabled = true; in smu_v13_0_6_set_default_dpm_table()
[all …]
A Daldebaran_ppt.h49 struct aldebaran_dpm_level dpm_levels[MAX_DPM_NUMBER]; member
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_2_ppt.c518 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
551 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
567 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
583 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
599 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
615 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
631 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
1129 single_dpm_table->dpm_levels[0].value); in smu_v14_0_2_print_clk_levels()
1133 single_dpm_table->dpm_levels[1].value); in smu_v14_0_2_print_clk_levels()
1136 single_dpm_table->dpm_levels[0].value, in smu_v14_0_2_print_clk_levels()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsienna_cichlid_ppt.c976 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
994 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
1012 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
1030 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
1093 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
1111 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
1129 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
2052 uint16_t *dpm_levels = NULL; in sienna_cichlid_get_uclk_dpm_states() local
2064 dpm_levels = table_member2; in sienna_cichlid_get_uclk_dpm_states()
2072 *clocks_in_khz = (*dpm_levels) * 1000; in sienna_cichlid_get_uclk_dpm_states()
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A Darcturus_ppt.c381 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
382 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
383 dpm_table->max = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
399 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
400 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
401 dpm_table->max = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
417 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
418 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
419 dpm_table->max = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
435 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
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A Dnavi10_ppt.c986 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
1004 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
1022 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
1040 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
1058 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
1076 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
1094 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
2306 uint16_t *dpm_levels = NULL; in navi10_get_uclk_dpm_states() local
2316 dpm_levels = driver_ppt->FreqTableUclk; in navi10_get_uclk_dpm_states()
2324 *clocks_in_khz = (*dpm_levels) * 1000; in navi10_get_uclk_dpm_states()
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A Darcturus_ppt.h49 struct arcturus_dpm_level dpm_levels[MAX_DPM_NUMBER]; member
/drivers/gpu/drm/radeon/
A Dci_dpm.c2573 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()
3338 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()
3346 dpm_table->dpm_levels[index].enabled = true; in ci_setup_pcie_table_entry()
3494 if (value == table->dpm_levels[i].value) { in ci_find_boot_level()
3660 dpm_table->dpm_levels[i].enabled = false; in ci_trim_single_dpm_states()
3662 dpm_table->dpm_levels[i].enabled = true; in ci_trim_single_dpm_states()
3681 pcie_table->dpm_levels[i].enabled = true; in ci_trim_pcie_dpm_states()
3685 if (pcie_table->dpm_levels[i].enabled) { in ci_trim_pcie_dpm_states()
3687 if (pcie_table->dpm_levels[j].enabled) { in ci_trim_pcie_dpm_states()
3688 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && in ci_trim_pcie_dpm_states()
[all …]
A Dci_dpm.h65 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dfiji_smumgr.c838 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in fiji_populate_smc_link_level()
840 dpm_table->pcie_speed_table.dpm_levels[i].param1); in fiji_populate_smc_link_level()
1024 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1235 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1239 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1316 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1374 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1395 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1535 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
1536 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
A Dpolaris10_smumgr.c827 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
829 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
1070 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1084 dpm_table->sclk_table.dpm_levels[0].value, in polaris10_populate_all_graphic_levels()
1091 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ? in polaris10_populate_all_graphic_levels()
1224 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1228 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1340 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1501 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
1502 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
[all …]
A Diceland_smumgr.c774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1364 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1625 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1764 data->dpm_table.mclk_table.dpm_levels[i].value, in iceland_convert_mc_reg_table_to_smc()
A Dvegam_smumgr.c581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
583 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
891 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
1050 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1054 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1290 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1291 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
A Dci_smumgr.c488 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
1007 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
1009 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
1317 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1319 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1663 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1664 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1799 data->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
A Dtonga_smumgr.c517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
1108 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1113 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1500 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
1501 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
2143 data->dpm_table.mclk_table.dpm_levels[i].value, in tonga_convert_mc_reg_table_to_smc()
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Dsmu_v14_0.h80 struct smu_14_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; member
A Dsmu_v11_0.h93 struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; member
A Dsmu_v13_0.h85 struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; member

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