| /drivers/gpu/drm/amd/display/dc/mpc/dcn10/ |
| A D | dcn10_mpc.c | 127 struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) in mpc1_get_mpcc_for_dpp() argument
132 if (tmp_mpcc->dpp_id == dpp_id) in mpc1_get_mpcc_for_dpp()
185 int dpp_id, in mpc1_insert_plane() argument
208 new_mpcc->dpp_id = dpp_id; in mpc1_insert_plane()
220 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); in mpc1_insert_plane()
325 mpcc_to_remove->dpp_id = 0xf; in mpc1_remove_mpcc()
339 mpcc->dpp_id = 0xf; in mpc1_init_mpcc()
422 mpcc->dpp_id = top_sel; in mpc1_init_mpcc_list_from_hw()
450 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc1_read_mpcc_state()
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| A D | dcn10_mpc.h | 147 int dpp_id,
190 int dpp_id);
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | mpc.h | 272 int dpp_id; member
325 uint32_t dpp_id; member
395 int dpp_id,
516 int dpp_id,
555 int dpp_id);
573 int dpp_id);
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 381 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect() local
392 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp_from_secondary(mpc_tree_params, dpp_id); in dcn201_plane_atomic_disconnect()
401 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id); in dcn201_plane_atomic_disconnect()
427 int mpcc_id, dpp_id; in dcn201_update_mpcc() local
481 dpp_id = hubp->inst; in dcn201_update_mpcc()
482 mpcc_id = dpp_id; in dcn201_update_mpcc()
493 remove_mpcc = mpc->funcs->get_mpcc_for_dpp_from_secondary(mpc_tree_params, dpp_id); in dcn201_update_mpcc()
500 remove_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id); in dcn201_update_mpcc()
517 dpp_id, in dcn201_update_mpcc()
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| A D | dcn20_mpc.c | 512 mpcc->dpp_id = 0xf; in mpc2_init_mpcc()
525 static struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) in mpc2_get_mpcc_for_dpp() argument
530 if (tmp_mpcc->dpp_id == 0xf || tmp_mpcc->dpp_id == dpp_id) in mpc2_get_mpcc_for_dpp()
551 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc2_read_mpcc_state()
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_mpc.c | 65 mpcc->dpp_id = 0xf; in mpc201_init_mpcc()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 402 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn10_get_mpcc_states()
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn30/ |
| A D | dcn30_mpc.c | 1052 mpcc->dpp_id = 0xf; in mpc3_init_mpcc()
1480 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc3_read_mpcc_state()
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| /drivers/scsi/lpfc/ |
| A D | lpfc_sli4.h | 241 uint16_t dpp_id; member
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| A D | lpfc_sli.c | 323 q->dpp_id); in lpfc_sli4_wq_put()
17049 wq->dpp_id = bf_get(lpfc_mbx_wq_create_dpp_id, in lpfc_wq_create()
17070 wq->dpp_id, dpp_barset, dpp_offset); in lpfc_wq_create()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| A D | dcn30_hwseq.c | 191 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn30_log_color_state()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 533 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn10_log_color_state()
1411 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn10_plane_atomic_disconnect() local
1418 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id); in dcn10_plane_atomic_disconnect()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 3701 if (s.dpp_id < MAX_MPCC) in acquire_resource_from_hw_enabled_state()
3702 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = in acquire_resource_from_hw_enabled_state()
3703 s.dpp_id; in acquire_resource_from_hw_enabled_state()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 174 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn20_log_color_state()
|