| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 933 if (pool->base.dpps[i] != NULL) in dcn201_resource_destruct()
934 dcn201_dpp_destroy(&pool->base.dpps[i]); in dcn201_resource_destruct()
1023 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1024 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn201_acquire_free_pipe_for_layer()
1221 pool->base.dpps[i] = dcn201_dpp_create(ctx, i); in dcn201_resource_construct()
1222 if (pool->base.dpps[i] == NULL) { in dcn201_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 923 if (pool->base.dpps[i] != NULL) in dcn10_resource_destruct()
924 dcn10_dpp_destroy(&pool->base.dpps[i]); in dcn10_resource_destruct()
1104 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_free_pipe_for_layer()
1105 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_free_pipe_for_layer()
1583 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); in dcn10_resource_construct()
1584 if (pool->base.dpps[j] == NULL) { in dcn10_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 1107 if (pool->base.dpps[i] != NULL) in dcn20_resource_destruct()
1108 dcn20_dpp_destroy(&pool->base.dpps[i]); in dcn20_resource_destruct()
1494 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1495 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1550 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1551 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in dcn20_split_stream_for_mpc()
2166 sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx]; in dcn20_acquire_free_pipe_for_layer()
2167 sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst; in dcn20_acquire_free_pipe_for_layer()
2633 pool->base.dpps[i] = dcn20_dpp_create(ctx, i); in dcn20_resource_construct()
2634 if (pool->base.dpps[i] == NULL) { in dcn20_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 1404 if (pool->base.dpps[i] != NULL) in dcn32_resource_destruct()
1405 dcn32_dpp_destroy(&pool->base.dpps[i]); in dcn32_resource_destruct()
2390 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); in dcn32_resource_construct()
2391 if (pool->base.dpps[j] == NULL) { in dcn32_resource_construct()
2761 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2762 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2820 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2822 pool->dpps[free_pipe->pipe_idx]->inst; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2853 free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2854 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst; in dcn32_acquire_free_pipe_as_secondary_opp_head()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 1022 if (pool->dpps[i] != NULL) { in dcn302_resource_destruct()
1023 kfree(TO_DCN20_DPP(pool->dpps[i])); in dcn302_resource_destruct()
1024 pool->dpps[i] = NULL; in dcn302_resource_destruct()
1379 pool->dpps[i] = dcn302_dpp_create(ctx, i); in dcn302_resource_construct()
1380 if (pool->dpps[i] == NULL) { in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 967 if (pool->dpps[i] != NULL) { in dcn303_resource_destruct()
968 kfree(TO_DCN20_DPP(pool->dpps[i])); in dcn303_resource_destruct()
969 pool->dpps[i] = NULL; in dcn303_resource_destruct()
1312 pool->dpps[i] = dcn303_dpp_create(ctx, i); in dcn303_resource_construct()
1313 if (pool->dpps[i] == NULL) { in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 678 if (pool->base.dpps[i] != NULL) in dcn21_resource_destruct()
679 dcn20_dpp_destroy(&pool->base.dpps[i]); in dcn21_resource_destruct()
1594 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); in dcn21_resource_construct()
1595 if (pool->base.dpps[j] == NULL) { in dcn21_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 1069 if (pool->base.dpps[i] != NULL) in dcn301_destruct()
1070 dcn301_dpp_destroy(&pool->base.dpps[i]); in dcn301_destruct()
1605 pool->base.dpps[j] = dcn301_dpp_create(ctx, i); in dcn301_resource_construct()
1606 if (pool->base.dpps[j] == NULL) { in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 1098 if (pool->base.dpps[i] != NULL) in dcn30_resource_destruct()
1099 dcn30_dpp_destroy(&pool->base.dpps[i]); in dcn30_resource_destruct()
1537 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1538 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
2477 pool->base.dpps[i] = dcn30_dpp_create(ctx, i); in dcn30_resource_construct()
2478 if (pool->base.dpps[i] == NULL) { in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 288 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw()
308 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 1395 if (pool->base.dpps[i] != NULL) in dcn316_resource_destruct()
1396 dcn31_dpp_destroy(&pool->base.dpps[i]); in dcn316_resource_destruct()
1900 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); in dcn316_resource_construct()
1901 if (pool->base.dpps[i] == NULL) { in dcn316_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 2539 split_pipe->plane_res.dpp = pool->dpps[i]; in acquire_first_split_pipe()
2541 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_split_pipe()
3690 pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]]; in acquire_resource_from_hw_enabled_state()
3693 if (pool->dpps[id_src[i]]) { in acquire_resource_from_hw_enabled_state()
3694 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst; in acquire_resource_from_hw_enabled_state()
3835 pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx]; in acquire_otg_master_pipe_for_stream()
3837 if (pool->dpps[pipe_idx]) in acquire_otg_master_pipe_for_stream()
3838 pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in acquire_otg_master_pipe_for_stream()
5459 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy()
5460 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 1457 if (pool->base.dpps[i] != NULL) in dcn314_resource_destruct()
1458 dcn31_dpp_destroy(&pool->base.dpps[i]); in dcn314_resource_destruct()
1999 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); in dcn314_resource_construct()
2000 if (pool->base.dpps[i] == NULL) { in dcn314_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 1399 if (pool->base.dpps[i] != NULL) in dcn31_resource_destruct()
1400 dcn31_dpp_destroy(&pool->base.dpps[i]); in dcn31_resource_destruct()
2076 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); in dcn31_resource_construct()
2077 if (pool->base.dpps[i] == NULL) { in dcn31_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 1386 if (pool->base.dpps[i] != NULL) in dcn321_resource_destruct()
1387 dcn321_dpp_destroy(&pool->base.dpps[i]); in dcn321_resource_destruct()
1892 pool->base.dpps[j] = dcn321_dpp_create(ctx, i); in dcn321_resource_construct()
1893 if (pool->base.dpps[j] == NULL) { in dcn321_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 1468 if (pool->base.dpps[i] != NULL) in dcn35_resource_destruct()
1469 dcn35_dpp_destroy(&pool->base.dpps[i]); in dcn35_resource_destruct()
2034 pool->base.dpps[i] = dcn35_dpp_create(ctx, i); in dcn35_resource_construct()
2035 if (pool->base.dpps[i] == NULL) { in dcn35_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 1399 if (pool->base.dpps[i] != NULL) in dcn315_resource_destruct()
1400 dcn31_dpp_destroy(&pool->base.dpps[i]); in dcn315_resource_destruct()
2024 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); in dcn315_resource_construct()
2025 if (pool->base.dpps[i] == NULL) { in dcn315_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 1448 if (pool->base.dpps[i] != NULL) in dcn351_resource_destruct()
1449 dcn35_dpp_destroy(&pool->base.dpps[i]); in dcn351_resource_destruct()
2005 pool->base.dpps[i] = dcn35_dpp_create(ctx, i); in dcn351_resource_construct()
2006 if (pool->base.dpps[i] == NULL) { in dcn351_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 1449 if (pool->base.dpps[i] != NULL) in dcn36_resource_destruct()
1450 dcn35_dpp_destroy(&pool->base.dpps[i]); in dcn36_resource_destruct()
2007 pool->base.dpps[i] = dcn35_dpp_create(ctx, i); in dcn36_resource_construct()
2008 if (pool->base.dpps[i] == NULL) { in dcn36_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 248 struct dpp *dpps[MAX_PIPES]; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 1407 if (pool->base.dpps[i] != NULL) in dcn401_resource_destruct()
1408 dcn401_dpp_destroy(&pool->base.dpps[i]); in dcn401_resource_destruct()
2083 pool->base.dpps[j] = dcn401_dpp_create(ctx, i); in dcn401_resource_construct()
2084 if (pool->base.dpps[j] == NULL) { in dcn401_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 343 struct dpp *dpp = pool->dpps[i]; in dcn10_get_cm_states()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr.c | 119 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst; in rn_update_clocks_update_dpp_dto()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 540 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
541 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in split_stream_across_pipes()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 89 struct dpp *dpp = pool->dpps[i]; in dcn20_log_color_state()
3163 struct dpp *dpp = res_pool->dpps[i]; in dcn20_fpga_init_hw()
3183 struct dpp *dpp = dc->res_pool->dpps[i]; in dcn20_fpga_init_hw()
|