| /drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| A D | dcn302_fpu.c | 176 dcn3_02_soc.dram_channel_width_bytes * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
179 dcn3_02_soc.dram_channel_width_bytes * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
214 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn302_fpu_update_bw_bounding_box()
215 dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn302_fpu_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| A D | dcn303_fpu.c | 174 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn303_get_optimal_dcfclk_fclk_for_uclk()
176 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn303_get_optimal_dcfclk_fclk_for_uclk()
210 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn303_fpu_update_bw_bounding_box()
211 dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn303_fpu_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| A D | dcn321_fpu.c | 150 .dram_channel_width_bytes = 2,
169 …dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixe… in get_optimal_ntuple()
175 …dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixe… in get_optimal_ntuple()
178 …dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixe… in get_optimal_ntuple()
193 …dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixe… in calculate_net_bw_in_kbytes_sec()
584 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn321_get_optimal_dcfclk_fclk_for_uclk()
586 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn321_get_optimal_dcfclk_fclk_for_uclk()
691 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn321_update_bw_bounding_box_fpu()
693 dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn321_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | dcn314_fpu.c | 156 .dram_channel_width_bytes = 4,
198 if (bw_params->dram_channel_width_bytes > 0) in dcn314_update_bw_bounding_box_fpu()
199 dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; in dcn314_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_policy.c | 38 …socbb->dram_channel_width_bytes * ((float)socbb->pct_ideal_dram_bw_after_urgent_pixel_only / 100)); in get_optimal_ntuple()
44 …socbb->dram_channel_width_bytes * ((float)socbb->pct_ideal_dram_bw_after_urgent_pixel_only / 100)); in get_optimal_ntuple()
47 …socbb->dram_channel_width_bytes * ((float)socbb->pct_ideal_dram_bw_after_urgent_pixel_only / 100)); in get_optimal_ntuple()
58 …socbb->dram_channel_width_bytes * ((float)socbb->pct_ideal_dram_bw_after_urgent_pixel_only / 100)); in calculate_net_bw_in_mbytes_sec()
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| A D | dml2_translation_helper.c | 268 out->dram_channel_width_bytes = 2; in dml2_init_socbb_params()
324 out->dram_channel_width_bytes = dml2->config.bbox_overrides.dram_chanel_width_bytes; in dml2_init_socbb_params()
685 out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes; in dml2_translate_socbb_params()
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| A D | display_mode_util.c | 675 dml_print("DML: soc_bbox: dram_channel_width_bytes = %d\n", soc->dram_channel_width_bytes); in dml_print_soc_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 175 .dram_channel_width_bytes = 4,
271 .dram_channel_width_bytes = 4,
419 .dram_channel_width_bytes = 4,
680 if (bw_params->dram_channel_width_bytes > 0) in dcn315_update_bw_bounding_box()
681 dcn3_15_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; in dcn315_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_socbb.h | 57 uint32_t dram_channel_width_bytes; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.c | 526 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn30_fpu_update_dram_channel_width_bytes()
527 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn30_fpu_update_dram_channel_width_bytes()
553 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()
555 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | clk_mgr.h | 262 unsigned int dram_channel_width_bytes; member
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| /drivers/gpu/drm/amd/display/include/ |
| A D | grph_object_ctrl_defs.h | 188 unsigned int dram_channel_width_bytes; member
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 290 if (dc_bw_params->dram_channel_width_bytes) { in override_dml_init_with_values_from_vbios()
291 dml_clk_table->dram_config.channel_width_bytes = dc_bw_params->dram_channel_width_bytes; in override_dml_init_with_values_from_vbios()
292 } else if (in_dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) { in override_dml_init_with_values_from_vbios()
293 …k_table->dram_config.channel_width_bytes = in_dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in override_dml_init_with_values_from_vbios()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 171 .dram_channel_width_bytes = 2,
372 dcn3_2_soc.dram_channel_width_bytes * in calculate_net_bw_in_kbytes_sec()
401 …dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_… in get_optimal_ntuple()
407 …dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_… in get_optimal_ntuple()
410 …dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_… in get_optimal_ntuple()
2641 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn32_get_optimal_dcfclk_fclk_for_uclk()
2643 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn32_get_optimal_dcfclk_fclk_for_uclk()
3133 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn32_update_bw_bounding_box_fpu()
3135 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn32_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_structs.h | 219 double dram_channel_width_bytes; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 191 .dram_channel_width_bytes = 4,
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| A D | bios_parser2.c | 2414 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; in get_vram_info_v23()
2433 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; in get_vram_info_v24()
2452 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; in get_vram_info_v25()
2471 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8; in get_vram_info_v30()
2490 info->dram_channel_width_bytes = (1 << info_v40->channel_width) / 8; in get_vram_info_from_umc_info_v40()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 213 .dram_channel_width_bytes = 4,/*not exist in dml2*/
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| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 175 .dram_channel_width_bytes = 4,/*not exist in dml2*/
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| A D | dcn316_clk_mgr.c | 550 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; in dcn316_clk_mgr_helper_populate_bw_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 310 .dram_channel_width_bytes = 2,
421 .dram_channel_width_bytes = 2,
532 .dram_channel_width_bytes = 16,
746 .dram_channel_width_bytes = 4,
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_clk_mgr.c | 571 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; in dcn315_clk_mgr_helper_populate_bw_params()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.c | 617 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; in dcn31_clk_mgr_helper_populate_bw_params()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| A D | dcn401_clk_mgr.c | 1424 …clk_mgr_base->bw_params->dram_channel_width_bytes = clk_mgr_base->ctx->dc_bios->vram_info.dram_cha… in dcn401_get_memclk_states_from_smu()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_clk_mgr.c | 738 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; in dcn314_clk_mgr_helper_populate_bw_params()
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